Simulation Results: entropy_src/rng_16bits

 
07/09/2026 15:31:36 DVSim: v1.52.1 sha: 6cca8d8 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 68.66 %
  • code
  • 82.23 %
  • assert
  • 74.20 %
  • func
  • 49.55 %
  • block
  • 94.08 %
  • line
  • 97.79 %
  • branch
  • 86.00 %
  • toggle
  • 52.41 %
  • FSM
  • 92.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 2.000s 60.696us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 2.000s 96.682us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 2.000s 48.361us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 23.000s 3321.729us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 3.000s 44.386us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
entropy_src_csr_mem_rw_with_rand_reset 2.000s 56.652us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 2.000s 48.361us 1 1 100.00
entropy_src_csr_aliasing 3.000s 44.386us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 2.000s 60.696us 1 1 100.00
entropy_src_rng 125.000s 13074.261us 1 1 100.00
entropy_src_fw_ov 237.000s 14111.129us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 237.000s 14111.129us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 125.000s 13074.261us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 69.000s 14153.514us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 125.000s 13074.261us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 125.000s 13074.261us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 125.000s 13074.261us 1 1 100.00
entropy_src_intr 18.000s 1344.652us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 125.000s 13074.261us 1 1 100.00
entropy_src_functional_alerts 7.000s 184.589us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 224.000s 13318.780us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 3.000s 42.834us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 10.000s 550.279us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 2.000s 33.159us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 65.226us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 7.000s 255.540us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 7.000s 255.540us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 96.682us 1 1 100.00
entropy_src_csr_rw 2.000s 48.361us 1 1 100.00
entropy_src_csr_aliasing 3.000s 44.386us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 22.880us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 96.682us 1 1 100.00
entropy_src_csr_rw 2.000s 48.361us 1 1 100.00
entropy_src_csr_aliasing 3.000s 44.386us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 22.880us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 2.000s 135.352us 1 1 100.00
entropy_src_tl_intg_err 4.000s 99.146us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 125.000s 13074.261us 1 1 100.00
entropy_src_cfg_regwen 2.000s 41.467us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 125.000s 13074.261us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 125.000s 13074.261us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 125.000s 13074.261us 1 1 100.00
entropy_src_fw_ov 237.000s 14111.129us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 3.000s 42.834us 1 1 100.00
entropy_src_sec_cm 2.000s 135.352us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 3.000s 42.834us 1 1 100.00
entropy_src_sec_cm 2.000s 135.352us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 125.000s 13074.261us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 3.000s 42.834us 1 1 100.00
entropy_src_sec_cm 2.000s 135.352us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 3.000s 42.834us 1 1 100.00
entropy_src_sec_cm 2.000s 135.352us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 3.000s 42.834us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 7.000s 184.589us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 4.000s 99.146us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 135.000s 13262.648us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 5.000s 519.474us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1661) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.alert_test 1 test run
entropy_src_stress_all_with_rand_reset 59655836829660615278193365807695703760089868541544190813241447623746542636991 165
UVM_INFO @ 519474419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---