Simulation Results: hmac

 
07/09/2026 15:31:36 DVSim: v1.52.1 sha: 6cca8d8 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 69.85 %
  • code
  • 83.23 %
  • assert
  • 96.96 %
  • func
  • 29.35 %
  • block
  • 97.51 %
  • line
  • 98.44 %
  • branch
  • 93.76 %
  • toggle
  • 45.89 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 16.000s 573.000us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.000s 242.106us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 1.000s 33.375us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 17.000s 476.196us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.000s 17.835us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.000s 21.810us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 1.000s 33.375us 1 1 100.00
hmac_csr_aliasing 2.000s 17.835us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 36.000s 7705.543us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 67.000s 1315.977us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 15.000s 239.924us 1 1 100.00
hmac_test_sha384_vectors 598.000s 18710.183us 1 1 100.00
hmac_test_sha512_vectors 32.000s 976.665us 1 1 100.00
hmac_test_hmac256_vectors 19.000s 4693.201us 1 1 100.00
hmac_test_hmac384_vectors 19.000s 438.396us 1 1 100.00
hmac_test_hmac512_vectors 25.000s 550.495us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 16.000s 5540.810us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 287.000s 70642.219us 1 1 100.00
error 1 1 100.00
hmac_error 52.000s 1194.863us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 122.000s 12341.376us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 16.000s 573.000us 1 1 100.00
hmac_long_msg 36.000s 7705.543us 1 1 100.00
hmac_back_pressure 67.000s 1315.977us 1 1 100.00
hmac_datapath_stress 287.000s 70642.219us 1 1 100.00
hmac_burst_wr 16.000s 5540.810us 1 1 100.00
hmac_stress_all 146.000s 55107.238us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 16.000s 573.000us 1 1 100.00
hmac_long_msg 36.000s 7705.543us 1 1 100.00
hmac_back_pressure 67.000s 1315.977us 1 1 100.00
hmac_datapath_stress 287.000s 70642.219us 1 1 100.00
hmac_wipe_secret 122.000s 12341.376us 1 1 100.00
hmac_test_sha256_vectors 15.000s 239.924us 1 1 100.00
hmac_test_sha384_vectors 598.000s 18710.183us 1 1 100.00
hmac_test_sha512_vectors 32.000s 976.665us 1 1 100.00
hmac_test_hmac256_vectors 19.000s 4693.201us 1 1 100.00
hmac_test_hmac384_vectors 19.000s 438.396us 1 1 100.00
hmac_test_hmac512_vectors 25.000s 550.495us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 16.000s 573.000us 1 1 100.00
hmac_long_msg 36.000s 7705.543us 1 1 100.00
hmac_back_pressure 67.000s 1315.977us 1 1 100.00
hmac_datapath_stress 287.000s 70642.219us 1 1 100.00
hmac_burst_wr 16.000s 5540.810us 1 1 100.00
hmac_error 52.000s 1194.863us 1 1 100.00
hmac_wipe_secret 122.000s 12341.376us 1 1 100.00
hmac_test_sha256_vectors 15.000s 239.924us 1 1 100.00
hmac_test_sha384_vectors 598.000s 18710.183us 1 1 100.00
hmac_test_sha512_vectors 32.000s 976.665us 1 1 100.00
hmac_test_hmac256_vectors 19.000s 4693.201us 1 1 100.00
hmac_test_hmac384_vectors 19.000s 438.396us 1 1 100.00
hmac_test_hmac512_vectors 25.000s 550.495us 1 1 100.00
hmac_stress_all 146.000s 55107.238us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 146.000s 55107.238us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 1.000s 20.997us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 1.000s 30.955us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.000s 104.136us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.000s 104.136us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.000s 242.106us 1 1 100.00
hmac_csr_rw 1.000s 33.375us 1 1 100.00
hmac_csr_aliasing 2.000s 17.835us 1 1 100.00
hmac_same_csr_outstanding 2.000s 80.032us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.000s 242.106us 1 1 100.00
hmac_csr_rw 1.000s 33.375us 1 1 100.00
hmac_csr_aliasing 2.000s 17.835us 1 1 100.00
hmac_same_csr_outstanding 2.000s 80.032us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 2.000s 41.643us 1 1 100.00
hmac_tl_intg_err 2.000s 100.282us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.000s 100.282us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 16.000s 573.000us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.000s 41.485us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 80.000s 2878.062us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.000s 24.868us 1 1 100.00