Simulation Results

Simulation Results: i2c

07/09/2026 15:31:36 DVSim: v1.52.1 sha: 6cca8d8 json Branch: master Tool: xcelium [24.03-s007]

Coverage statistics

Total
87.63 %

code
85.59 %

assert
97.25 %

func
80.07 %

block
95.87 %

line
95.23 %

branch
92.58 %

toggle
72.52 %

FSM
82.01 %

Validation stages

V1		100.00%
V2		80.49%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	315.000s	6576.239us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	16.000s	1129.160us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	2.000s	67.624us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	2.000s	74.471us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	8.000s	4270.100us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	2.000s	63.784us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	2.000s	73.078us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	2.000s	74.471us	1	1	100.00
	i2c_csr_aliasing	2.000s	63.784us	1	1	100.00

33/41 passed

80.49 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	2.000s	27.181us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	3601.000s	0.000us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	63.000s	5116.186us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	1.000s	22.080us	1	1	100.00
host_fifo_watermark				0	1	0.00
	i2c_host_fifo_watermark	3602.149s	0.000us	0	1	0.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	1806.000s	3198.260us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	2.000s	158.832us	1	1	100.00
	i2c_host_fifo_fmt_empty	29.000s	1205.612us	1	1	100.00
	i2c_host_fifo_reset_rx	5.000s	198.247us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	1999.000s	3373.046us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	39.000s	872.712us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	2.000s	98.923us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	5.000s	800.698us	0	1	0.00
target_stress_all				0	1	0.00
	i2c_target_stress_all	3601.000s	0.000us	0	1	0.00
target_maxperf				1	1	100.00
	i2c_target_perf	8.000s	3906.444us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	24.000s	4583.101us	1	1	100.00
	i2c_target_intr_smoke	12.000s	1081.035us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	2.000s	303.964us	1	1	100.00
	i2c_target_fifo_reset_tx	3.000s	250.668us	1	1	100.00
target_fifo_full				2	3	66.67
	i2c_target_stress_wr	3600.000s	0.000us	0	1	0.00
	i2c_target_stress_rd	24.000s	4583.101us	1	1	100.00
	i2c_target_intr_stress_wr	1340.000s	37008.493us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	10.000s	16093.559us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	1004.000s	4425.476us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	7.000s	843.469us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	6.000s	10044.375us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	5.000s	3226.066us	1	1	100.00
	i2c_target_fifo_watermarks_tx	2.000s	205.482us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	63.000s	5116.186us	1	1	100.00
	i2c_host_perf_precise	2.000s	300.892us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	39.000s	872.712us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	3.000s	98.750us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	5.000s	702.278us	1	1	100.00
	i2c_target_nack_acqfull_addr	4.000s	1936.428us	1	1	100.00
	i2c_target_nack_txstretch	3.000s	165.460us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	16.000s	1862.018us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	4.000s	952.251us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	2.000s	66.777us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	1.000s	22.140us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	3.000s	76.191us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	3.000s	76.191us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	2.000s	67.624us	1	1	100.00
	i2c_csr_rw	2.000s	74.471us	1	1	100.00
	i2c_csr_aliasing	2.000s	63.784us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	37.827us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	2.000s	67.624us	1	1	100.00
	i2c_csr_rw	2.000s	74.471us	1	1	100.00
	i2c_csr_aliasing	2.000s	63.784us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	37.827us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	3.000s	558.825us	1	1	100.00
	i2c_sec_cm	2.000s	40.971us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	3.000s	558.825us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	13.000s	1040.852us	1
target_error_intr				1
	i2c_target_unexp_stop	2.000s	50.788us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	8.000s	604.282us	1

Error Messages

	Test	seed	line	log context
Job timed out after * minutes				4 test runs
	i2c_host_fifo_watermark	58065922849464131844731043320711915588018530443468928140449023525904401933573	None
	i2c_host_stress_all	13759923583060769218139161629066616392668250532432872975437277843892812767930	None
	i2c_target_stress_wr	44509689776253514213207270118848845615051803269899421537881603043116586819184	None
	i2c_target_stress_all	19255001452201161285872911711417637316538758573280910895506060388604688586196	None
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				2 test runs
	i2c_host_error_intr	11421989472975534205217985339181809082465535583576393481025802101127908300763	89	UVM_INFO @ 27181107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_mode_toggle	114475010891941238883769291740056502251611383104507381001794931044161995071024	90	UVM_INFO @ 98922946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1297) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	i2c_host_stress_all_with_rand_reset	81003918059606003381336681106221614507146031135364035634497200694196153748285	112	UVM_INFO @ 1040851793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	107454581521673626252781434973668743635018319816393823731553969829125545711829	103	UVM_INFO @ 604281797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	33174267799474215473158569805877785040257312973634136305895108090405745938843	93	UVM_INFO @ 800698433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:680) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	69017659545076893629984949278203956858597103695924014345681467602682843239205	87	UVM_INFO @ 50787512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	5485930965642362066789476517977352152401534595671999025454515022440415019514	88	UVM_INFO @ 10044374894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---