Simulation Results

Simulation Results: keymgr_dpe/darjeeling

07/09/2026 15:31:36 DVSim: v1.52.1 sha: 6cca8d8 json Branch: master Tool: xcelium [24.03-s007]

Coverage statistics

Total
65.55 %

code
82.33 %

assert
96.96 %

func
17.37 %

block
97.98 %

line
98.66 %

branch
93.43 %

toggle
55.69 %

FSM
81.54 %

Validation stages

V1		100.00%
V2		100.00%
V2S		100.00%

V1

6/6 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	keymgr_dpe_smoke	17.000s	2270.057us	1	1	100.00
csr_hw_reset				1	1	100.00
	keymgr_dpe_csr_hw_reset	2.000s	11.503us	1	1	100.00
csr_rw				1	1	100.00
	keymgr_dpe_csr_rw	2.000s	26.625us	1	1	100.00
csr_bit_bash				1	1	100.00
	keymgr_dpe_csr_bit_bash	7.000s	894.430us	1	1	100.00
csr_aliasing				1	1	100.00
	keymgr_dpe_csr_aliasing	3.000s	190.876us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	keymgr_dpe_csr_mem_rw_with_rand_reset	2.000s	31.067us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	keymgr_dpe_csr_rw	2.000s	26.625us	1	1	100.00
	keymgr_dpe_csr_aliasing	3.000s	190.876us	1	1	100.00

V2

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
intr_test				1	1	100.00
	keymgr_dpe_intr_test	2.000s	11.016us	1	1	100.00
alert_test				1	1	100.00
	keymgr_dpe_alert_test	1.000s	14.398us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	keymgr_dpe_tl_errors	2.000s	22.524us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	keymgr_dpe_tl_errors	2.000s	22.524us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	keymgr_dpe_csr_hw_reset	2.000s	11.503us	1	1	100.00
	keymgr_dpe_csr_rw	2.000s	26.625us	1	1	100.00
	keymgr_dpe_csr_aliasing	3.000s	190.876us	1	1	100.00
	keymgr_dpe_same_csr_outstanding	3.000s	89.632us	1	1	100.00
tl_d_partial_access				4	4	100.00
	keymgr_dpe_csr_hw_reset	2.000s	11.503us	1	1	100.00
	keymgr_dpe_csr_rw	2.000s	26.625us	1	1	100.00
	keymgr_dpe_csr_aliasing	3.000s	190.876us	1	1	100.00
	keymgr_dpe_same_csr_outstanding	3.000s	89.632us	1	1	100.00

V2S

4/4 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	keymgr_dpe_sec_cm	8.000s	756.056us	1	1	100.00
	keymgr_dpe_tl_intg_err	4.000s	114.150us	1	1	100.00
shadow_reg_update_error				1	1	100.00
	keymgr_dpe_shadow_reg_errors	3.000s	93.561us	1	1	100.00
shadow_reg_read_clear_staged_value				1	1	100.00
	keymgr_dpe_shadow_reg_errors	3.000s	93.561us	1	1	100.00
shadow_reg_storage_error				1	1	100.00
	keymgr_dpe_shadow_reg_errors	3.000s	93.561us	1	1	100.00
shadowed_reset_glitch				1	1	100.00
	keymgr_dpe_shadow_reg_errors	3.000s	93.561us	1	1	100.00
shadow_reg_update_error_with_csr_rw				1	1	100.00
	keymgr_dpe_shadow_reg_errors_with_csr_rw	4.000s	188.423us	1	1	100.00
prim_count_check				1	1	100.00
	keymgr_dpe_sec_cm	8.000s	756.056us	1	1	100.00
prim_fsm_check				1	1	100.00
	keymgr_dpe_sec_cm	8.000s	756.056us	1	1	100.00