Simulation Results: lc_ctrl/volatile_unlock_disabled

 
07/09/2026 15:31:36 DVSim: v1.52.1 sha: 6cca8d8 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 88.49 %
  • code
  • 89.94 %
  • assert
  • 96.83 %
  • func
  • 78.71 %
  • block
  • 95.89 %
  • line
  • 96.48 %
  • branch
  • 89.54 %
  • toggle
  • 83.27 %
  • FSM
  • 90.48 %
Validation stages
V1
100.00%
V2
73.33%
V2S
70.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 17.686us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 25.741us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 63.945us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 3.000s 198.829us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 19.919us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 38.452us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 63.945us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 19.919us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.000s 1236.039us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 8.000s 233.902us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 49.009us 1 1 100.00
lc_prog_failure 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_errors 0 1 0.00
lc_ctrl_errors 3601.000s 0.000us 0 1 0.00
security_escalation 1 7 14.29
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_errors 3601.000s 0.000us 0 1 0.00
lc_ctrl_security_escalation 9.000s 2250.353us 1 1 100.00
lc_ctrl_jtag_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3601.000s 0.000us 0 1 0.00
jtag_access 10 13 76.92
lc_ctrl_jtag_smoke 5.000s 493.938us 1 1 100.00
lc_ctrl_jtag_state_post_trans 4.000s 225.060us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3601.000s 0.000us 0 1 0.00
lc_ctrl_jtag_access 4.000s 430.790us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 11.000s 820.883us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 201.584us 1 1 100.00
lc_ctrl_jtag_csr_rw 3.000s 304.396us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.000s 1453.864us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.000s 2003.056us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 185.035us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.000s 273.087us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 26.842us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 6.000s 566.428us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 15.175us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 10804.438s 0.000us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 43.776us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 4.000s 108.430us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 4.000s 108.430us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 25.741us 1 1 100.00
lc_ctrl_csr_rw 2.000s 63.945us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 19.919us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.000s 30.326us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 25.741us 1 1 100.00
lc_ctrl_csr_rw 2.000s 63.945us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 19.919us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.000s 30.326us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 268.259us 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 230.807us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 230.807us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 8.000s 233.902us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 268.259us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 268.259us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 268.259us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 268.259us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 268.259us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 268.259us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 268.259us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 268.259us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 9.000s 2250.353us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 1 2 50.00
lc_ctrl_state_post_trans 3.000s 1236.039us 1 1 100.00
lc_ctrl_jtag_state_post_trans 4.000s 225.060us 0 1 0.00
sec_cm_intersig_mubi 0 1 0.00
lc_ctrl_sec_mubi 3601.000s 0.000us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
lc_ctrl_sec_mubi 3601.000s 0.000us 0 1 0.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.000s 459.551us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.000s 3276.068us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.000s 3276.068us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3600.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 9 test runs
lc_ctrl_state_failure 55227567058044175983090939630234383679122733980114949427839365446396514791709 None
lc_ctrl_prog_failure 99492528376951623728405852452262101155664043602716140547914344874988225146969 None
lc_ctrl_errors 45697224543453425512315460850525472368747843329832728908220127005193650008504 None
lc_ctrl_jtag_state_failure 51805225244543251944099410499533239081149112780656835490124924492715472816698 None
lc_ctrl_jtag_prog_failure 62747861864707847370384408240320022639741254936364483277606948907719707085475 None
lc_ctrl_jtag_errors 108986846672488336202482251658480131454722677072328685375215322555625342219403 None
lc_ctrl_sec_mubi 11271680146712509068713705628602988577476335091239137962857648098391339228289 None
lc_ctrl_stress_all 102803610511824070372694943113519593994005249640947349611628964890719653273760 None
lc_ctrl_stress_all_with_rand_reset 91784984599703187203168892459654952211541961557932083629676827369657863650215 None
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 1 test run
lc_ctrl_jtag_state_post_trans 60299091461143512308622204493444879237099816879649721632322845737396518051373 236
UVM_INFO @ 225060329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---