Simulation Results: lc_ctrl/volatile_unlock_enabled

 
07/09/2026 15:31:36 DVSim: v1.52.1 sha: 6cca8d8 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 88.10 %
  • code
  • 89.41 %
  • assert
  • 96.83 %
  • func
  • 78.06 %
  • block
  • 96.39 %
  • line
  • 97.18 %
  • branch
  • 90.85 %
  • toggle
  • 79.11 %
  • FSM
  • 90.48 %
Validation stages
V1
100.00%
V2
70.00%
V2S
60.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 3.000s 114.257us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 57.657us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 27.085us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 3.000s 118.588us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 59.437us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.000s 64.897us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 27.085us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 59.437us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 7.000s 4369.113us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 22.104us 1 1 100.00
lc_prog_failure 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_errors 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
security_escalation 1 7 14.29
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_security_escalation 4.000s 183.770us 1 1 100.00
lc_ctrl_jtag_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3601.000s 0.000us 0 1 0.00
jtag_access 10 13 76.92
lc_ctrl_jtag_smoke 4.000s 1784.052us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3601.000s 0.000us 0 1 0.00
lc_ctrl_jtag_access 9.000s 9825.399us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 12.000s 904.058us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 370.074us 1 1 100.00
lc_ctrl_jtag_csr_rw 3.000s 58.991us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 12.000s 2380.492us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.000s 95.894us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 259.185us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 880.883us 1 1 100.00
lc_ctrl_jtag_alert_test 3.000s 72.578us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.000s 731.594us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 21.216us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 10802.097s 0.000us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 16.825us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 29.208us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 29.208us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 57.657us 1 1 100.00
lc_ctrl_csr_rw 1.000s 27.085us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 59.437us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 30.400us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 57.657us 1 1 100.00
lc_ctrl_csr_rw 1.000s 27.085us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 59.437us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 30.400us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 841.944us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 74.212us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 74.212us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 7.000s 4369.113us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 841.944us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 841.944us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 841.944us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 841.944us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 841.944us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 841.944us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 841.944us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 841.944us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.000s 183.770us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
sec_cm_intersig_mubi 0 1 0.00
lc_ctrl_sec_mubi 3601.000s 0.000us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
lc_ctrl_sec_mubi 3601.000s 0.000us 0 1 0.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.000s 774.867us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 239.141us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 239.141us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3600.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 11 test runs
lc_ctrl_state_failure 111855184398261398825671812295865716399262812390271277634055182280372471546353 None
lc_ctrl_state_post_trans 65500047438522660879121901693539865948966335742595588818400074530194431528973 None
lc_ctrl_prog_failure 63107045348161009776842780019302595542795312485764485632122808066372631428537 None
lc_ctrl_errors 28284642950057537275362444809074005351386150650414354010946823711989378037098 None
lc_ctrl_jtag_state_failure 80009324023297740393123706977209671163249917150455322002747110252739950526831 None
lc_ctrl_jtag_state_post_trans 60371775471726529968093656661769837122614227856054147254501535854521896451619 None
lc_ctrl_jtag_prog_failure 23636979778458853077646108292335421742245862987520514483407121348186691572616 None
lc_ctrl_jtag_errors 9134794386117067244110417345082471551986403553061624889334827498316311075404 None
lc_ctrl_sec_mubi 35069983532660282763389970977593509235997595836126089002621008221902178687879 None
lc_ctrl_stress_all 53058792561586601268913316131762837235174491516228838923162721093017926407430 None
lc_ctrl_stress_all_with_rand_reset 94997511597651007483214975207010797765795182669512840620152577792983587016725 None