Simulation Results: otp_ctrl

 
07/09/2026 15:31:36 DVSim: v1.52.1 sha: 6cca8d8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 67.53 %
  • code
  • 66.64 %
  • assert
  • 90.92 %
  • func
  • 45.04 %
  • line
  • 84.80 %
  • branch
  • 78.70 %
  • cond
  • 83.29 %
  • toggle
  • 60.45 %
  • FSM
  • 25.95 %
Validation stages
V1
77.78%
V2
45.00%
V2S
11.11%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.560s 59.372us 1 1 100.00
smoke 0 1 0.00
otp_ctrl_smoke 3.050s 124.331us 0 1 0.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 3.650s 118.595us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 2.800s 93.287us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 7.520s 340.097us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 3.850s 1348.955us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.070s 64.776us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 2.800s 93.287us 1 1 100.00
otp_ctrl_csr_aliasing 3.850s 1348.955us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 2.250s 84.749us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 2.110s 101.098us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 170.090s 15359.730us 0 1 0.00
init_fail 0 1 0.00
otp_ctrl_init_fail 6.360s 2949.193us 0 1 0.00
partition_check 0 2 0.00
otp_ctrl_background_chks 31.580s 8456.891us 0 1 0.00
otp_ctrl_check_fail 11.310s 1108.970us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 12.490s 556.850us 1 1 100.00
partition_lock 0 1 0.00
otp_ctrl_dai_lock 2.460s 220.017us 0 1 0.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 33.930s 7981.494us 1 1 100.00
lc_interactions 0 2 0.00
otp_ctrl_parallel_lc_req 10.740s 966.370us 0 1 0.00
otp_ctrl_parallel_lc_esc 4.830s 430.375us 0 1 0.00
otp_dai_errors 0 1 0.00
otp_ctrl_dai_errs 11.050s 1339.850us 0 1 0.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 3.320s 356.006us 0 1 0.00
test_access 0 1 0.00
otp_ctrl_test_access 5.080s 243.338us 0 1 0.00
stress_all 0 1 0.00
otp_ctrl_stress_all 24.120s 3358.923us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 3.050s 644.787us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.440s 52.640us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 3.420s 131.592us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 3.420s 131.592us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.650s 118.595us 1 1 100.00
otp_ctrl_csr_rw 2.800s 93.287us 1 1 100.00
otp_ctrl_csr_aliasing 3.850s 1348.955us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.810s 1019.266us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.650s 118.595us 1 1 100.00
otp_ctrl_csr_rw 2.800s 93.287us 1 1 100.00
otp_ctrl_csr_aliasing 3.850s 1348.955us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.810s 1019.266us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 0 1 0.00
otp_ctrl_sec_cm 35.510s 14273.267us 0 1 0.00
tl_intg_err 0 2 0.00
otp_ctrl_sec_cm 35.510s 14273.267us 0 1 0.00
otp_ctrl_tl_intg_err 5.750s 2685.132us 0 1 0.00
prim_count_check 0 1 0.00
otp_ctrl_sec_cm 35.510s 14273.267us 0 1 0.00
prim_fsm_check 0 1 0.00
otp_ctrl_sec_cm 35.510s 14273.267us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
otp_ctrl_tl_intg_err 5.750s 2685.132us 0 1 0.00
sec_cm_secret_mem_scramble 0 1 0.00
otp_ctrl_smoke 3.050s 124.331us 0 1 0.00
sec_cm_part_mem_digest 0 1 0.00
otp_ctrl_smoke 3.050s 124.331us 0 1 0.00
sec_cm_dai_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 35.510s 14273.267us 0 1 0.00
sec_cm_kdi_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 35.510s 14273.267us 0 1 0.00
sec_cm_lci_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 35.510s 14273.267us 0 1 0.00
sec_cm_part_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 35.510s 14273.267us 0 1 0.00
sec_cm_scrmbl_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 35.510s 14273.267us 0 1 0.00
sec_cm_timer_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 35.510s 14273.267us 0 1 0.00
sec_cm_dai_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 35.510s 14273.267us 0 1 0.00
sec_cm_kdi_seed_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 35.510s 14273.267us 0 1 0.00
sec_cm_kdi_entropy_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 35.510s 14273.267us 0 1 0.00
sec_cm_lci_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 35.510s 14273.267us 0 1 0.00
sec_cm_part_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 35.510s 14273.267us 0 1 0.00
sec_cm_scrmbl_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 35.510s 14273.267us 0 1 0.00
sec_cm_timer_integ_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 35.510s 14273.267us 0 1 0.00
sec_cm_timer_cnsty_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 35.510s 14273.267us 0 1 0.00
sec_cm_timer_lfsr_redun 0 1 0.00
otp_ctrl_sec_cm 35.510s 14273.267us 0 1 0.00
sec_cm_dai_fsm_local_esc 0 2 0.00
otp_ctrl_parallel_lc_esc 4.830s 430.375us 0 1 0.00
otp_ctrl_sec_cm 35.510s 14273.267us 0 1 0.00
sec_cm_lci_fsm_local_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 4.830s 430.375us 0 1 0.00
sec_cm_kdi_fsm_local_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 4.830s 430.375us 0 1 0.00
sec_cm_part_fsm_local_esc 0 2 0.00
otp_ctrl_parallel_lc_esc 4.830s 430.375us 0 1 0.00
otp_ctrl_macro_errs 3.320s 356.006us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 4.830s 430.375us 0 1 0.00
sec_cm_timer_fsm_local_esc 0 2 0.00
otp_ctrl_parallel_lc_esc 4.830s 430.375us 0 1 0.00
otp_ctrl_sec_cm 35.510s 14273.267us 0 1 0.00
sec_cm_dai_fsm_global_esc 0 2 0.00
otp_ctrl_parallel_lc_esc 4.830s 430.375us 0 1 0.00
otp_ctrl_sec_cm 35.510s 14273.267us 0 1 0.00
sec_cm_lci_fsm_global_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 4.830s 430.375us 0 1 0.00
sec_cm_kdi_fsm_global_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 4.830s 430.375us 0 1 0.00
sec_cm_part_fsm_global_esc 0 2 0.00
otp_ctrl_parallel_lc_esc 4.830s 430.375us 0 1 0.00
otp_ctrl_macro_errs 3.320s 356.006us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 4.830s 430.375us 0 1 0.00
sec_cm_timer_fsm_global_esc 0 2 0.00
otp_ctrl_parallel_lc_esc 4.830s 430.375us 0 1 0.00
otp_ctrl_sec_cm 35.510s 14273.267us 0 1 0.00
sec_cm_part_data_reg_integrity 0 1 0.00
otp_ctrl_init_fail 6.360s 2949.193us 0 1 0.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 11.310s 1108.970us 0 1 0.00
sec_cm_part_mem_regren 0 1 0.00
otp_ctrl_dai_lock 2.460s 220.017us 0 1 0.00
sec_cm_part_mem_sw_unreadable 0 1 0.00
otp_ctrl_dai_lock 2.460s 220.017us 0 1 0.00
sec_cm_part_mem_sw_unwritable 0 1 0.00
otp_ctrl_dai_lock 2.460s 220.017us 0 1 0.00
sec_cm_lc_part_mem_sw_noaccess 0 1 0.00
otp_ctrl_dai_lock 2.460s 220.017us 0 1 0.00
sec_cm_access_ctrl_mubi 0 1 0.00
otp_ctrl_dai_lock 2.460s 220.017us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
otp_ctrl_smoke 3.050s 124.331us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 0 1 0.00
otp_ctrl_dai_lock 2.460s 220.017us 0 1 0.00
sec_cm_test_bus_lc_gated 0 1 0.00
otp_ctrl_smoke 3.050s 124.331us 0 1 0.00
sec_cm_test_tl_lc_gate_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 35.510s 14273.267us 0 1 0.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 12.490s 556.850us 1 1 100.00
sec_cm_check_trigger_config_regwen 0 1 0.00
otp_ctrl_smoke 3.050s 124.331us 0 1 0.00
sec_cm_check_config_regwen 0 1 0.00
otp_ctrl_smoke 3.050s 124.331us 0 1 0.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 3.320s 356.006us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 214.550s 62642.074us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 11.560s 2988.116us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 4 test runs
otp_ctrl_parallel_lc_esc 58983433664782018168195820620416811230722301687050536206468678360647519080582 1458
UVM_INFO @ 430374688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 61278329385626676508198759844660868146498998089200753607936342256250304685803 166
UVM_INFO @ 220017219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 80071958440763178688910055017815244188354152104688900946045036108779284701445 4850
UVM_INFO @ 1339850286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_test_access 83603735715431124392041401653921391148343171667022803739053672538757265194193 1921
UVM_INFO @ 243338032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 2 test runs
otp_ctrl_background_chks 44037976921931076177297061499038377665246709306146549146803486892056421413997 16831
UVM_INFO @ 8456890915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 5646977944779239015266495452203472612399277678760027392668263475848239348475 10781
UVM_INFO @ 3358923055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 2 test runs
otp_ctrl_check_fail 14629348640525675181524772325375483849108930539076733841479668533139528147698 4055
UVM_INFO @ 1108969664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 99609459576652733077246846074138187149705819167530857972521221162579049663420 462
UVM_INFO @ 356006309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:786) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 2 test runs
otp_ctrl_stress_all_with_rand_reset 114439836034060355323742195821536437363241691658092220711962165669260264431255 499
UVM_INFO @ 2988115996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_csr_mem_rw_with_rand_reset 112805882274218722198157316632914918108716402370684912019098797740636811637758 97
UVM_INFO @ 64776085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * 1 test run
otp_ctrl_smoke 71202578424867322382422051129362655991919809312635357276150635739586403709388 356
UVM_INFO @ 124330609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_partition_walk_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_partition_walk 57464912889000199406215433926489751165119722656976606830658717288969088830067 110147
UVM_INFO @ 15359730190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_low_freq_read 99428611853419593921285924613119312405768564374210358496557109531171576697818 95
UVM_INFO @ 62642074043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1375) [otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger! 1 test run
otp_ctrl_init_fail 86970559931086275339495383482365362863481813012836109676833011244444095265053 1912
UVM_INFO @ 2949192895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:961) [scoreboard] Check failed (csr.get_mirrored_value() | status_mask) == (item.d_data | status_mask) (* [*] vs * [*]) reg name: status, compare_mask * 1 test run
otp_ctrl_parallel_lc_req 6160291332445154266007138426298226974133974055322701505212939390540666186004 6106
UVM_INFO @ 966369598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [otp_ctrl_common_vseq] Expected alert (fatal_check_error) did not fire in * cycles. 1 test run
otp_ctrl_sec_cm 102482230337375870915312712887165863318177991139181056825171063524311073346779 281
UVM_INFO @ 14273267024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [otp_ctrl_common_vseq] Expected alert (fatal_bus_integ_error) did not fire in * cycles. 1 test run
otp_ctrl_tl_intg_err 57888981091951306892760083758181641033893665327690813250731489717614651351707 128
UVM_INFO @ 2685131515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---