Simulation Results: rom_ctrl/32kb

 
07/09/2026 15:31:36 DVSim: v1.52.1 sha: 6cca8d8 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 90.33 %
  • code
  • 79.72 %
  • assert
  • 97.67 %
  • func
  • 93.59 %
  • block
  • 78.48 %
  • line
  • 78.74 %
  • branch
  • 79.30 %
  • toggle
  • 84.65 %
  • FSM
  • 76.19 %
Validation stages
V1
100.00%
V2
77.78%
V2S
66.67%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.000s 591.176us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.000s 59.844us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.000s 52.298us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.000s 72.318us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 61.250us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 2.000s 60.077us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.000s 52.298us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 61.250us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 2.000s 66.640us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 2.000s 55.398us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 3.000s 172.990us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 7.000s 572.664us 1 1 100.00
kmac_err_chk 0 1 0.00
rom_ctrl_kmac_err_chk 3600.000s 0.000us 0 1 0.00
alert_test 1 1 100.00
rom_ctrl_alert_test 2.000s 74.872us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 6.000s 737.473us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 6.000s 737.473us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.000s 59.844us 1 1 100.00
rom_ctrl_csr_rw 3.000s 52.298us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 61.250us 1 1 100.00
rom_ctrl_same_csr_outstanding 2.000s 111.926us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.000s 59.844us 1 1 100.00
rom_ctrl_csr_rw 3.000s 52.298us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 61.250us 1 1 100.00
rom_ctrl_same_csr_outstanding 2.000s 111.926us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 6.000s 84.489us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 70.000s 232.203us 1 1 100.00
rom_ctrl_tl_intg_err 16.000s 128.212us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 70.000s 232.203us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 70.000s 232.203us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 70.000s 232.203us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 70.000s 232.203us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.000s 591.176us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.000s 591.176us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.000s 591.176us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 16.000s 128.212us 1 1 100.00
sec_cm_bus_local_esc 0 2 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 1 0.00
rom_ctrl_kmac_err_chk 3600.000s 0.000us 0 1 0.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 6.000s 84.489us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 70.000s 232.203us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rom_ctrl_stress_all_with_rand_reset 20.000s 957.173us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
rom_ctrl_corrupt_sig_fatal_chk 22975366935304452335759260952194769317645126133326879789689177974208738115964 None
rom_ctrl_kmac_err_chk 15886274592832081503217652276937610357771078156533840346261883427450456069837 None
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 758175087271353216379406449439855779743199849738430007786923764583131940974 88
UVM_INFO @ 172990313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:425) scoreboard [scoreboard] Waited * cycles but did not see alert fatal. (Max wait calculated ALERT_B2B_DELAY + max_delay + * = * + * + *) 1 test run
rom_ctrl_stress_all_with_rand_reset 9996502909463207733044443610842407682238086209209062146417973617922393413001 110
UVM_INFO @ 957173094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---