Simulation Results: rstmgr

 
07/09/2026 15:31:36 DVSim: v1.52.1 sha: 6cca8d8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.08 %
  • code
  • 99.12 %
  • assert
  • 98.72 %
  • func
  • 96.39 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.07 %
  • toggle
  • 99.52 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.870s 69.019us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.420s 63.217us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 1.250s 36.378us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 3.530s 82.214us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.230s 36.868us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 2.220s 95.768us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 1.250s 36.378us 1 1 100.00
rstmgr_csr_aliasing 1.230s 36.868us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.720s 142.179us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.530s 44.942us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.280s 70.823us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 6.580s 729.268us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 6.580s 729.268us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 6.580s 729.268us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 6.580s 729.268us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 12.780s 1829.462us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.230s 37.387us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.520s 41.329us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.520s 41.329us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.420s 63.217us 1 1 100.00
rstmgr_csr_rw 1.250s 36.378us 1 1 100.00
rstmgr_csr_aliasing 1.230s 36.868us 1 1 100.00
rstmgr_same_csr_outstanding 1.480s 47.428us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.420s 63.217us 1 1 100.00
rstmgr_csr_rw 1.250s 36.378us 1 1 100.00
rstmgr_csr_aliasing 1.230s 36.868us 1 1 100.00
rstmgr_same_csr_outstanding 1.480s 47.428us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 58.150s 6762.997us 1 1 100.00
rstmgr_tl_intg_err 4.360s 335.748us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 58.150s 6762.997us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 58.150s 6762.997us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 4.360s 335.748us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.560s 60.139us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 4.500s 478.123us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 3.170s 291.585us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 58.150s 6762.997us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 1.250s 36.378us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 1.250s 36.378us 1 1 100.00