Simulation Results: rv_timer

 
07/09/2026 15:31:36 DVSim: v1.52.1 sha: 6cca8d8 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 95.82 %
  • code
  • 90.09 %
  • assert
  • 97.78 %
  • func
  • 99.58 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 71.98 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.000s 197.363us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 49.783us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 2.000s 14.441us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.000s 345.156us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 2.000s 25.117us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 2.000s 37.440us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 2.000s 14.441us 1 1 100.00
rv_timer_csr_aliasing 2.000s 25.117us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 1 1 100.00
rv_timer_random_reset 2.000s 275.421us 1 1 100.00
disabled 1 1 100.00
rv_timer_disabled 3.000s 2107.491us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 125.000s 289269.719us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 125.000s 289269.719us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 10.000s 949.977us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 1.000s 19.187us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 1.000s 72.166us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.000s 228.503us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.000s 228.503us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 49.783us 1 1 100.00
rv_timer_csr_rw 2.000s 14.441us 1 1 100.00
rv_timer_csr_aliasing 2.000s 25.117us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 42.133us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 49.783us 1 1 100.00
rv_timer_csr_rw 2.000s 14.441us 1 1 100.00
rv_timer_csr_aliasing 2.000s 25.117us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 42.133us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 2.000s 114.755us 1 1 100.00
rv_timer_tl_intg_err 2.000s 157.712us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 2.000s 157.712us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 1.000s 67.414us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 2.000s 164.616us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 3.000s 565.907us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:183) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 1 test run
rv_timer_min 97400385757375258088722092804795501933310125157536009000973854282580028160578 84
UVM_INFO @ 67413801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:227) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 59454490325059194633219304047548079699438835844518814256206247256432415763880 84
UVM_INFO @ 164616095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---