Simulation Results: spi_device/1r1w

 
07/09/2026 15:31:36 DVSim: v1.52.1 sha: 6cca8d8 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 84.19 %
  • code
  • 89.52 %
  • assert
  • 95.40 %
  • func
  • 67.66 %
  • block
  • 98.35 %
  • line
  • 98.75 %
  • branch
  • 97.01 %
  • toggle
  • 72.75 %
  • FSM
  • 89.58 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 40.000s 2023.553us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 3.000s 37.854us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 3.000s 158.255us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 25.000s 524.946us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 3.000s 35.426us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 5.000s 283.500us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 3.000s 158.255us 1 1 100.00
spi_device_csr_aliasing 3.000s 35.426us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 1.000s 15.595us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 3.000s 190.338us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 2.000s 13.605us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 2.000s 3.289us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 2.000s 11.059us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 4.000s 126.092us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 4.000s 126.092us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 23.000s 2044.355us 1 1 100.00
spi_device_tpm_sts_read 2.000s 22.034us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 9.000s 738.741us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 27.000s 2443.704us 1 1 100.00
spi_device_flash_all 67.000s 8470.159us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 10.000s 799.638us 1 1 100.00
spi_device_flash_all 67.000s 8470.159us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 10.000s 799.638us 1 1 100.00
spi_device_flash_all 67.000s 8470.159us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 67.000s 8470.159us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 3.000s 34.522us 1 1 100.00
spi_device_flash_all 67.000s 8470.159us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 3.000s 34.522us 1 1 100.00
spi_device_flash_all 67.000s 8470.159us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 3.000s 34.522us 1 1 100.00
spi_device_flash_all 67.000s 8470.159us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 3.000s 34.522us 1 1 100.00
spi_device_flash_all 67.000s 8470.159us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 3.000s 34.522us 1 1 100.00
spi_device_flash_all 67.000s 8470.159us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 7.000s 275.308us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 90.000s 23312.711us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 90.000s 23312.711us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 90.000s 23312.711us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 8.000s 273.743us 1 1 100.00
spi_device_read_buffer_direct 5.000s 344.385us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 90.000s 23312.711us 1 1 100.00
spi_device_flash_all 67.000s 8470.159us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 67.000s 8470.159us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 67.000s 8470.159us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 12.000s 1960.069us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 12.000s 1960.069us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 318.000s 26034.424us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 40.000s 2023.553us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 80.000s 5971.257us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 267.000s 59390.219us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 1.000s 20.122us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 2.000s 25.573us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.000s 32.943us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.000s 32.943us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 3.000s 37.854us 1 1 100.00
spi_device_csr_rw 3.000s 158.255us 1 1 100.00
spi_device_csr_aliasing 3.000s 35.426us 1 1 100.00
spi_device_same_csr_outstanding 6.000s 172.909us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 3.000s 37.854us 1 1 100.00
spi_device_csr_rw 3.000s 158.255us 1 1 100.00
spi_device_csr_aliasing 3.000s 35.426us 1 1 100.00
spi_device_same_csr_outstanding 6.000s 172.909us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 2.000s 81.792us 1 1 100.00
spi_device_tl_intg_err 12.000s 1599.500us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 12.000s 1599.500us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
spi_device_mem_parity 110965834109239823008932051448900023777791732938881665011998295267726347388730 87
UVM_ERROR @ 2189427 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
ERROR: VHPI NOTFOUND
Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[913] not found within the scope .
UVM_ERROR @ 2189427 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[913] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 50603488270641694828894961193965829371139203472212911437307486224419663464803 85
UVM_ERROR @ 8594403 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x12d [100101101] vs 0x0 [0])
UVM_ERROR @ 8693403 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3ed [1111101101] vs 0x0 [0])
UVM_ERROR @ 8709403 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x127 [100100111] vs 0x0 [0])
UVM_ERROR @ 8747403 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x304 [1100000100] vs 0x0 [0])