Simulation Results: sram_ctrl/ret

 
07/09/2026 15:31:36 DVSim: v1.52.1 sha: 6cca8d8 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 90.77 %
  • code
  • 81.37 %
  • assert
  • 97.95 %
  • func
  • 93.00 %
  • block
  • 91.85 %
  • line
  • 93.41 %
  • branch
  • 87.60 %
  • toggle
  • 77.79 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 432.925us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 43.183us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 40.202us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 224.358us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 20.686us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 121.637us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 40.202us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 20.686us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 7.000s 684.900us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 5.000s 88.042us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 7.000s 430.260us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 180.000s 7153.227us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 8.000s 583.451us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 18.000s 2207.976us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 7.000s 508.373us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 7.000s 350.575us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 184.666us 1 1 100.00
sram_ctrl_partial_access_b2b 223.000s 9033.721us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 2.000s 37.744us 1 1 100.00
sram_ctrl_throughput_w_partial_write 2.000s 46.308us 1 1 100.00
sram_ctrl_throughput_w_readback 2.000s 163.832us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 3.000s 67.641us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 28.997us 1 1 100.00
non_pow2_mem_size 3 3 100.00
sram_ctrl_smoke 2.000s 432.925us 1 1 100.00
sram_ctrl_partial_access 2.000s 184.666us 1 1 100.00
sram_ctrl_access_during_key_req 18.000s 2207.976us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 44.000s 3561.218us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 46.615us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 6.000s 143.073us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 6.000s 143.073us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 43.183us 1 1 100.00
sram_ctrl_csr_rw 2.000s 40.202us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 20.686us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 25.982us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 43.183us 1 1 100.00
sram_ctrl_csr_rw 2.000s 40.202us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 20.686us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 25.982us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 5.000s 1477.319us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 776.528us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 547.157us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 776.528us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 547.157us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 3.000s 67.641us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 3.000s 67.641us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 40.202us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 7.000s 350.575us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 7.000s 350.575us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 7.000s 350.575us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 7.000s 508.373us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3601.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 5.000s 1477.319us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 432.925us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 432.925us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 7.000s 350.575us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 776.528us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 7.000s 508.373us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 776.528us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 776.528us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 432.925us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 776.528us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 63.000s 5771.667us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 2017230856793707949460128325677550703877335355911498305293755975634876625037 None
sram_ctrl_mubi_enc_err 87554558136089940210800152910863188324104210649440054656450284741831482421089 None