Simulation Results

Simulation Results: uart

07/09/2026 15:31:36 DVSim: v1.52.1 sha: 6cca8d8 json Branch: master Tool: xcelium [24.03-s007]

Coverage statistics

Total
93.70 %

code
92.73 %

assert
97.69 %

func
90.69 %

block
99.08 %

line
99.52 %

branch
98.34 %

toggle
73.08 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		95.45%
V2S		100.00%
V3		100.00%

6/6 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	uart_smoke	2.000s	251.818us	1	1	100.00
csr_hw_reset				1	1	100.00
	uart_csr_hw_reset	1.000s	46.773us	1	1	100.00
csr_rw				1	1	100.00
	uart_csr_rw	1.000s	13.504us	1	1	100.00
csr_bit_bash				1	1	100.00
	uart_csr_bit_bash	4.000s	598.799us	1	1	100.00
csr_aliasing				1	1	100.00
	uart_csr_aliasing	1.000s	29.144us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	uart_csr_mem_rw_with_rand_reset	2.000s	76.918us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	uart_csr_rw	1.000s	13.504us	1	1	100.00
	uart_csr_aliasing	1.000s	29.144us	1	1	100.00

21/22 passed

95.45 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
base_random_seq				1	1	100.00
	uart_tx_rx	90.000s	95931.829us	1	1	100.00
parity				2	2	100.00
	uart_smoke	2.000s	251.818us	1	1	100.00
	uart_tx_rx	90.000s	95931.829us	1	1	100.00
parity_error				2	2	100.00
	uart_intr	53.000s	22412.481us	1	1	100.00
	uart_rx_parity_err	110.000s	134840.367us	1	1	100.00
watermark				2	2	100.00
	uart_tx_rx	90.000s	95931.829us	1	1	100.00
	uart_intr	53.000s	22412.481us	1	1	100.00
fifo_full				1	1	100.00
	uart_fifo_full	308.000s	149369.310us	1	1	100.00
fifo_overflow				1	1	100.00
	uart_fifo_overflow	44.000s	69826.319us	1	1	100.00
fifo_reset				1	1	100.00
	uart_fifo_reset	149.000s	94858.187us	1	1	100.00
rx_frame_err				1	1	100.00
	uart_intr	53.000s	22412.481us	1	1	100.00
rx_break_err				1	1	100.00
	uart_intr	53.000s	22412.481us	1	1	100.00
rx_timeout				1	1	100.00
	uart_intr	53.000s	22412.481us	1	1	100.00
perf				1	1	100.00
	uart_perf	211.000s	8020.678us	1	1	100.00
sys_loopback				1	1	100.00
	uart_loopback	4.000s	3392.272us	1	1	100.00
line_loopback				1	1	100.00
	uart_loopback	4.000s	3392.272us	1	1	100.00
rx_noise_filter				0	1	0.00
	uart_noise_filter	8.000s	4013.631us	0	1	0.00
rx_start_bit_filter				1	1	100.00
	uart_rx_start_bit_filter	3.000s	3820.872us	1	1	100.00
tx_overide				1	1	100.00
	uart_tx_ovrd	5.000s	1483.310us	1	1	100.00
rx_oversample				1	1	100.00
	uart_rx_oversample	7.000s	5691.061us	1	1	100.00
long_b2b_transfer				1	1	100.00
	uart_long_xfer_wo_dly	839.000s	131191.322us	1	1	100.00
stress_all				1	1	100.00
	uart_stress_all	31.000s	48599.870us	1	1	100.00
alert_test				1	1	100.00
	uart_alert_test	1.000s	12.767us	1	1	100.00
intr_test				1	1	100.00
	uart_intr_test	1.000s	21.703us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	uart_tl_errors	3.000s	412.854us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	uart_tl_errors	3.000s	412.854us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	uart_csr_hw_reset	1.000s	46.773us	1	1	100.00
	uart_csr_rw	1.000s	13.504us	1	1	100.00
	uart_csr_aliasing	1.000s	29.144us	1	1	100.00
	uart_same_csr_outstanding	2.000s	23.128us	1	1	100.00
tl_d_partial_access				4	4	100.00
	uart_csr_hw_reset	1.000s	46.773us	1	1	100.00
	uart_csr_rw	1.000s	13.504us	1	1	100.00
	uart_csr_aliasing	1.000s	29.144us	1	1	100.00
	uart_same_csr_outstanding	2.000s	23.128us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	uart_sec_cm	1.000s	40.946us	1	1	100.00
	uart_tl_intg_err	2.000s	274.710us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	uart_tl_intg_err	2.000s	274.710us	1	1	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	1	100.00
	uart_stress_all_with_rand_reset	29.000s	9423.670us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uart_scoreboard.sv:392) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [] vs []) check rx_idle fail: rx_en = , uart_rx_clk_pulses = *				1 test run
	uart_noise_filter	76733262208392738986529468312817352792890116780918453029130663946427571696125	85	UVM_ERROR @ 4000620075 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 4000817998 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 4001318014 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 4001495103 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0