Simulation Results: aes/gcm_masked

 
08/09/2026 15:31:51 DVSim: v1.52.1 sha: 82334bf json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 86.70 %
  • code
  • 95.61 %
  • assert
  • 98.29 %
  • func
  • 66.21 %
  • block
  • 95.74 %
  • line
  • 97.43 %
  • branch
  • 89.52 %
  • toggle
  • 98.05 %
  • FSM
  • 97.42 %
Validation stages
V1
100.00%
V2
100.00%
V2S
88.89%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 3.000s 95.583us 1 1 100.00
smoke 1 1 100.00
aes_smoke 4.000s 153.689us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 64.540us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 3.000s 67.011us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 8.000s 641.224us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 136.804us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 120.805us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 3.000s 67.011us 1 1 100.00
aes_csr_aliasing 2.000s 136.804us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 4.000s 153.689us 1 1 100.00
aes_config_error 4.000s 146.508us 1 1 100.00
aes_stress 6.000s 211.664us 1 1 100.00
key_length 3 3 100.00
aes_smoke 4.000s 153.689us 1 1 100.00
aes_config_error 4.000s 146.508us 1 1 100.00
aes_stress 6.000s 211.664us 1 1 100.00
back2back 2 2 100.00
aes_stress 6.000s 211.664us 1 1 100.00
aes_b2b 16.000s 1031.048us 1 1 100.00
backpressure 1 1 100.00
aes_stress 6.000s 211.664us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 4.000s 153.689us 1 1 100.00
aes_config_error 4.000s 146.508us 1 1 100.00
aes_stress 6.000s 211.664us 1 1 100.00
aes_alert_reset 3.000s 95.075us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 3.000s 72.014us 1 1 100.00
aes_config_error 4.000s 146.508us 1 1 100.00
aes_alert_reset 3.000s 95.075us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 7.000s 258.867us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 12.000s 617.661us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 12.000s 2452.378us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 95.075us 1 1 100.00
stress 1 1 100.00
aes_stress 6.000s 211.664us 1 1 100.00
sideload 2 2 100.00
aes_stress 6.000s 211.664us 1 1 100.00
aes_sideload 5.000s 150.190us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 5.000s 88.719us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 20.000s 1241.501us 1 1 100.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 3.000s 82.724us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 60.499us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 103.126us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 103.126us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 64.540us 1 1 100.00
aes_csr_rw 3.000s 67.011us 1 1 100.00
aes_csr_aliasing 2.000s 136.804us 1 1 100.00
aes_same_csr_outstanding 3.000s 78.922us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 64.540us 1 1 100.00
aes_csr_rw 3.000s 67.011us 1 1 100.00
aes_csr_aliasing 2.000s 136.804us 1 1 100.00
aes_same_csr_outstanding 3.000s 78.922us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 6.000s 160.219us 1 1 100.00
fault_inject 1 3 33.33
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 61.000s 0.000us 0 1 0.00
aes_cipher_fi 3.000s 49.100us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 75.679us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 75.679us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 75.679us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 75.679us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 140.335us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 5.000s 544.574us 1 1 100.00
aes_tl_intg_err 4.000s 354.307us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 4.000s 354.307us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 95.075us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 75.679us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 75.679us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 4.000s 153.689us 1 1 100.00
aes_stress 6.000s 211.664us 1 1 100.00
aes_alert_reset 3.000s 95.075us 1 1 100.00
aes_core_fi 3.000s 246.860us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 3.000s 82.724us 1 1 100.00
aes_config_error 4.000s 146.508us 1 1 100.00
aes_stress 6.000s 211.664us 1 1 100.00
aes_core_fi 3.000s 246.860us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 75.679us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 3.000s 78.896us 1 1 100.00
aes_stress 6.000s 211.664us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 6.000s 211.664us 1 1 100.00
aes_sideload 5.000s 150.190us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 3.000s 78.896us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 3.000s 78.896us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 3.000s 78.896us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 3.000s 78.896us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 3.000s 78.896us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 6.000s 211.664us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 6.000s 211.664us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3601.000s 0.000us 0 1 0.00
sec_cm_main_fsm_redun 2 4 50.00
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 61.000s 0.000us 0 1 0.00
aes_cipher_fi 3.000s 49.100us 1 1 100.00
aes_ctr_fi 2.000s 53.276us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3601.000s 0.000us 0 1 0.00
sec_cm_cipher_fsm_redun 1 3 33.33
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 61.000s 0.000us 0 1 0.00
aes_cipher_fi 3.000s 49.100us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 49.100us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3601.000s 0.000us 0 1 0.00
sec_cm_ctr_fsm_redun 1 3 33.33
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 61.000s 0.000us 0 1 0.00
aes_ctr_fi 2.000s 53.276us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3601.000s 0.000us 0 1 0.00
sec_cm_ctrl_sparse 2 4 50.00
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 61.000s 0.000us 0 1 0.00
aes_cipher_fi 3.000s 49.100us 1 1 100.00
aes_ctr_fi 2.000s 53.276us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 95.075us 1 1 100.00
sec_cm_main_fsm_local_esc 2 4 50.00
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 61.000s 0.000us 0 1 0.00
aes_cipher_fi 3.000s 49.100us 1 1 100.00
aes_ctr_fi 2.000s 53.276us 1 1 100.00
sec_cm_cipher_fsm_local_esc 2 4 50.00
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 61.000s 0.000us 0 1 0.00
aes_cipher_fi 3.000s 49.100us 1 1 100.00
aes_ctr_fi 2.000s 53.276us 1 1 100.00
sec_cm_ctr_fsm_local_esc 1 3 33.33
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 61.000s 0.000us 0 1 0.00
aes_ctr_fi 2.000s 53.276us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_ghash_fi 3.000s 56.351us 1 1 100.00
aes_fi 3601.000s 0.000us 0 1 0.00
sec_cm_data_reg_local_esc 1 3 33.33
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 61.000s 0.000us 0 1 0.00
aes_cipher_fi 3.000s 49.100us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 20.000s 10942.246us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
aes_fi 60027920359951053645200856230948637527762090431254614408911676509663204188723 None
aes_control_fi 16832610365226261886875434421670815883484991951434747393224178785327499865566 None
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_stress_all_with_rand_reset 103474999867143427389677976278623973092312038038514816662996359634911756448437 236
UVM_INFO @ 10942246270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---