Simulation Results: aes/gcm_unmasked

 
08/09/2026 15:31:51 DVSim: v1.52.1 sha: 82334bf json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 84.47 %
  • code
  • 91.31 %
  • assert
  • 97.75 %
  • func
  • 64.35 %
  • block
  • 90.79 %
  • line
  • 92.61 %
  • branch
  • 83.85 %
  • toggle
  • 97.99 %
  • FSM
  • 90.78 %
Validation stages
V1
100.00%
V2
88.24%
V2S
81.25%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 55.233us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 66.828us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 100.021us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 60.270us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 7.000s 2405.490us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 1.000s 70.540us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 72.799us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 60.270us 1 1 100.00
aes_csr_aliasing 1.000s 70.540us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 66.828us 1 1 100.00
aes_config_error 4.000s 138.253us 1 1 100.00
aes_stress 4.000s 420.579us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 66.828us 1 1 100.00
aes_config_error 4.000s 138.253us 1 1 100.00
aes_stress 4.000s 420.579us 1 1 100.00
back2back 2 2 100.00
aes_stress 4.000s 420.579us 1 1 100.00
aes_b2b 3.000s 75.880us 1 1 100.00
backpressure 1 1 100.00
aes_stress 4.000s 420.579us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 3.000s 66.828us 1 1 100.00
aes_config_error 4.000s 138.253us 1 1 100.00
aes_stress 4.000s 420.579us 1 1 100.00
aes_alert_reset 3602.227s 0.000us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 3.000s 66.991us 1 1 100.00
aes_config_error 4.000s 138.253us 1 1 100.00
aes_alert_reset 3602.227s 0.000us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 4.000s 111.039us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 5.000s 387.714us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 3602.227s 0.000us 0 1 0.00
stress 1 1 100.00
aes_stress 4.000s 420.579us 1 1 100.00
sideload 2 2 100.00
aes_stress 4.000s 420.579us 1 1 100.00
aes_sideload 3.000s 92.051us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 73.677us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 6.000s 349.193us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 61.430us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 5.000s 489.641us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 5.000s 489.641us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 100.021us 1 1 100.00
aes_csr_rw 2.000s 60.270us 1 1 100.00
aes_csr_aliasing 1.000s 70.540us 1 1 100.00
aes_same_csr_outstanding 2.000s 110.149us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 100.021us 1 1 100.00
aes_csr_rw 2.000s 60.270us 1 1 100.00
aes_csr_aliasing 1.000s 70.540us 1 1 100.00
aes_same_csr_outstanding 2.000s 110.149us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 281.723us 1 1 100.00
fault_inject 1 3 33.33
aes_fi 4.000s 131.033us 0 1 0.00
aes_control_fi 3.000s 66.168us 1 1 100.00
aes_cipher_fi 35.000s 10002.889us 0 1 0.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 236.347us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 236.347us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 236.347us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 236.347us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 112.810us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 671.492us 1 1 100.00
aes_tl_intg_err 3.000s 335.564us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 335.564us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 3602.227s 0.000us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 236.347us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 236.347us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 3.000s 66.828us 1 1 100.00
aes_stress 4.000s 420.579us 1 1 100.00
aes_alert_reset 3602.227s 0.000us 0 1 0.00
aes_core_fi 3.000s 298.564us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 4.000s 138.253us 1 1 100.00
aes_stress 4.000s 420.579us 1 1 100.00
aes_core_fi 3.000s 298.564us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 236.347us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 82.479us 1 1 100.00
aes_stress 4.000s 420.579us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 4.000s 420.579us 1 1 100.00
aes_sideload 3.000s 92.051us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 82.479us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 82.479us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 82.479us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 82.479us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 82.479us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 4.000s 420.579us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 4.000s 420.579us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 4.000s 131.033us 0 1 0.00
sec_cm_main_fsm_redun 2 4 50.00
aes_fi 4.000s 131.033us 0 1 0.00
aes_control_fi 3.000s 66.168us 1 1 100.00
aes_cipher_fi 35.000s 10002.889us 0 1 0.00
aes_ctr_fi 2.000s 62.501us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 4.000s 131.033us 0 1 0.00
sec_cm_cipher_fsm_redun 1 3 33.33
aes_fi 4.000s 131.033us 0 1 0.00
aes_control_fi 3.000s 66.168us 1 1 100.00
aes_cipher_fi 35.000s 10002.889us 0 1 0.00
sec_cm_cipher_ctr_redun 0 1 0.00
aes_cipher_fi 35.000s 10002.889us 0 1 0.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 4.000s 131.033us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 4.000s 131.033us 0 1 0.00
aes_control_fi 3.000s 66.168us 1 1 100.00
aes_ctr_fi 2.000s 62.501us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 4.000s 131.033us 0 1 0.00
sec_cm_ctrl_sparse 2 4 50.00
aes_fi 4.000s 131.033us 0 1 0.00
aes_control_fi 3.000s 66.168us 1 1 100.00
aes_cipher_fi 35.000s 10002.889us 0 1 0.00
aes_ctr_fi 2.000s 62.501us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 3602.227s 0.000us 0 1 0.00
sec_cm_main_fsm_local_esc 2 4 50.00
aes_fi 4.000s 131.033us 0 1 0.00
aes_control_fi 3.000s 66.168us 1 1 100.00
aes_cipher_fi 35.000s 10002.889us 0 1 0.00
aes_ctr_fi 2.000s 62.501us 1 1 100.00
sec_cm_cipher_fsm_local_esc 2 4 50.00
aes_fi 4.000s 131.033us 0 1 0.00
aes_control_fi 3.000s 66.168us 1 1 100.00
aes_cipher_fi 35.000s 10002.889us 0 1 0.00
aes_ctr_fi 2.000s 62.501us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 4.000s 131.033us 0 1 0.00
aes_control_fi 3.000s 66.168us 1 1 100.00
aes_ctr_fi 2.000s 62.501us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 4.000s 131.033us 0 1 0.00
sec_cm_data_reg_local_esc 1 3 33.33
aes_fi 4.000s 131.033us 0 1 0.00
aes_control_fi 3.000s 66.168us 1 1 100.00
aes_cipher_fi 35.000s 10002.889us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 3.000s 20.657us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 1 test run
aes_alert_reset 34880170087882708047410039817883975788610935783397863169437894289648661453689 None
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 1 test run
aes_fi 87572528316937275274298494295380578601026555533127133841137685330116326580190 6022
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 4
----| Seen: 3
----| Expected corrupted: 0
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! 1 test run
aes_cipher_fi 23608010102995741331376858347219812344034269508997497625487695039375612036602 144
UVM_INFO @ 10002889175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error 1 test run
aes_stress_all 30541410521247080852262731905170155343625342880769900857523698118303705721068 16340
UVM_INFO @ 349193174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_stress_all_with_rand_reset 29931386628675244433478749323805387131788891193377217454426798373376400472912 176
UVM_INFO @ 20656731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---