Simulation Results: clkmgr

 
08/09/2026 15:31:51 DVSim: v1.52.1 sha: 82334bf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 77.43 %
  • code
  • 69.71 %
  • assert
  • 90.50 %
  • func
  • 72.09 %
  • line
  • 82.32 %
  • branch
  • 87.53 %
  • cond
  • 79.45 %
  • toggle
  • 99.25 %
  • FSM
  • 0.00 %
Validation stages
V1
50.00%
V2
61.54%
V2S
50.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 2.200s 73.896us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.020s 30.501us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 1.140s 48.743us 1 1 100.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 1.760s 35.304us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.750s 3.364us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 0.780s 7.798us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 1 2 50.00
clkmgr_csr_rw 1.140s 48.743us 1 1 100.00
clkmgr_csr_aliasing 0.750s 3.364us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 1.200s 19.868us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.920s 75.129us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.880s 17.882us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 2.200s 73.896us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.860s 6.261us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.770s 7.799us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.860s 6.261us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 1.570s 82.057us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 0.920s 17.957us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 6.700s 415.075us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 6.700s 415.075us 1 1 100.00
tl_d_outstanding_access 2 4 50.00
clkmgr_csr_hw_reset 1.020s 30.501us 1 1 100.00
clkmgr_csr_rw 1.140s 48.743us 1 1 100.00
clkmgr_csr_aliasing 0.750s 3.364us 0 1 0.00
clkmgr_same_csr_outstanding 0.940s 8.000us 0 1 0.00
tl_d_partial_access 2 4 50.00
clkmgr_csr_hw_reset 1.020s 30.501us 1 1 100.00
clkmgr_csr_rw 1.140s 48.743us 1 1 100.00
clkmgr_csr_aliasing 0.750s 3.364us 0 1 0.00
clkmgr_same_csr_outstanding 0.940s 8.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 2.770s 155.651us 1 1 100.00
clkmgr_tl_intg_err 1.110s 12.417us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 3.930s 202.854us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 3.930s 202.854us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 3.930s 202.854us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 3.930s 202.854us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 1.110s 10.155us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 1.110s 12.417us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.860s 6.261us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.770s 7.799us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 3.930s 202.854us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.400s 80.859us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 1.140s 48.743us 1 1 100.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 2.770s 155.651us 1 1 100.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 1.140s 48.743us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 1.140s 48.743us 1 1 100.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 2.770s 155.651us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.710s 7.460us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 2.000s 55.373us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 3 test runs
clkmgr_frequency_timeout 2968731025760835159890851140646094181197597840020466932212843915790468194000 84
UVM_INFO @ 7798694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 53471563719354948894935573287071743835480489408509252044078428942571333990727 85
UVM_INFO @ 55372983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 56628202201100652468758847893814350191383966665375434216384473299109670627318 231
UVM_INFO @ 82056712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 2 test runs
clkmgr_shadow_reg_errors_with_csr_rw 101342634390501212067936267933997534523676413744646459650580315008560382021860 81
UVM_INFO @ 10155419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 104538153938725601881744982482821570248273666718113903110973578148270945516555 84
UVM_INFO @ 12417454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 2 test runs
clkmgr_csr_aliasing 19859267972664984543165142182877606906945124996116364489179233858172843447184 84
UVM_INFO @ 3363541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 14882123147473201428482228193299997241390091129439810150955202276370192610963 82
UVM_INFO @ 7797795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 1 test run
clkmgr_frequency 7698758232253580146900692804773096678356942745320561761982193503624699215616 81
UVM_INFO @ 6260520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:254) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed 1 test run
clkmgr_regwen 87579271542137765270180678059744650509081450914821361325666058809103872698760 80
UVM_INFO @ 7459962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 4713268399282047234629326865818228848826136202893251845798158498590168127955 81
UVM_INFO @ 35304455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 54843004135700265481196920360952610088704678712330867971889026973763164971319 81
UVM_INFO @ 7999907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---