Simulation Results: edn/edn0

 
08/09/2026 15:31:51 DVSim: v1.52.1 sha: 82334bf json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 78.98 %
  • code
  • 90.02 %
  • assert
  • 97.12 %
  • func
  • 49.79 %
  • block
  • 95.47 %
  • line
  • 97.71 %
  • branch
  • 90.14 %
  • toggle
  • 81.54 %
  • FSM
  • 90.70 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 2.000s 36.703us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.000s 20.153us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.000s 62.201us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 5.000s 338.536us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 2.000s 19.849us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 2.000s 39.280us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.000s 62.201us 1 1 100.00
edn_csr_aliasing 2.000s 19.849us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.000s 123.890us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.000s 123.890us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.000s 123.890us 1 1 100.00
interrupts 1 1 100.00
edn_intr 2.000s 96.423us 1 1 100.00
alerts 1 1 100.00
edn_alert 2.000s 43.358us 1 1 100.00
errs 1 1 100.00
edn_err 2.000s 53.215us 1 1 100.00
disable 2 2 100.00
edn_disable 2.000s 40.668us 1 1 100.00
edn_disable_auto_req_mode 3.000s 394.373us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 9.000s 302.115us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 2.000s 56.817us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 2.000s 19.604us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.000s 41.491us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.000s 41.491us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.000s 20.153us 1 1 100.00
edn_csr_rw 1.000s 62.201us 1 1 100.00
edn_csr_aliasing 2.000s 19.849us 1 1 100.00
edn_same_csr_outstanding 2.000s 46.289us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.000s 20.153us 1 1 100.00
edn_csr_rw 1.000s 62.201us 1 1 100.00
edn_csr_aliasing 2.000s 19.849us 1 1 100.00
edn_same_csr_outstanding 2.000s 46.289us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 10.000s 658.082us 1 1 100.00
edn_tl_intg_err 2.000s 191.615us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 2.000s 26.398us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 2.000s 43.358us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 10.000s 658.082us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 10.000s 658.082us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 10.000s 658.082us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 10.000s 658.082us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 2.000s 43.358us 1 1 100.00
edn_sec_cm 10.000s 658.082us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 2.000s 43.358us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.000s 191.615us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 42.000s 1609.159us 1 1 100.00