Simulation Results: edn/edn1

 
08/09/2026 15:31:51 DVSim: v1.52.1 sha: 82334bf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.82 %
  • code
  • 83.91 %
  • assert
  • 98.18 %
  • func
  • 78.36 %
  • line
  • 97.80 %
  • branch
  • 92.86 %
  • cond
  • 90.38 %
  • toggle
  • 95.31 %
  • FSM
  • 43.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.130s 39.614us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.170s 18.434us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.110s 36.865us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 8.740s 1274.948us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.200s 27.258us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.720s 93.217us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.110s 36.865us 1 1 100.00
edn_csr_aliasing 1.200s 27.258us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.330s 51.132us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.330s 51.132us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.330s 51.132us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.060s 20.569us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.460s 28.583us 1 1 100.00
errs 1 1 100.00
edn_err 1.470s 47.506us 1 1 100.00
disable 2 2 100.00
edn_disable 1.170s 13.434us 1 1 100.00
edn_disable_auto_req_mode 1.800s 53.167us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.250s 425.641us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.220s 19.203us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.070s 42.108us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.430s 235.625us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.430s 235.625us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.170s 18.434us 1 1 100.00
edn_csr_rw 1.110s 36.865us 1 1 100.00
edn_csr_aliasing 1.200s 27.258us 1 1 100.00
edn_same_csr_outstanding 1.850s 137.811us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.170s 18.434us 1 1 100.00
edn_csr_rw 1.110s 36.865us 1 1 100.00
edn_csr_aliasing 1.200s 27.258us 1 1 100.00
edn_same_csr_outstanding 1.850s 137.811us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 4.820s 310.300us 1 1 100.00
edn_tl_intg_err 2.930s 183.486us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.230s 20.150us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.460s 28.583us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.820s 310.300us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.820s 310.300us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 4.820s 310.300us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 4.820s 310.300us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.460s 28.583us 1 1 100.00
edn_sec_cm 4.820s 310.300us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.460s 28.583us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.930s 183.486us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 26.760s 2115.607us 1 1 100.00