Simulation Results: entropy_src/rng_16bits

 
08/09/2026 15:31:51 DVSim: v1.52.1 sha: 82334bf json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 69.54 %
  • code
  • 82.01 %
  • assert
  • 73.92 %
  • func
  • 52.68 %
  • block
  • 94.09 %
  • line
  • 97.77 %
  • branch
  • 86.07 %
  • toggle
  • 52.53 %
  • FSM
  • 91.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 3.000s 59.446us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 2.000s 31.268us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 2.000s 18.379us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 23.000s 2578.483us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 3.000s 45.717us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
entropy_src_csr_mem_rw_with_rand_reset 3.000s 31.703us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 2.000s 18.379us 1 1 100.00
entropy_src_csr_aliasing 3.000s 45.717us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 3.000s 59.446us 1 1 100.00
entropy_src_rng 264.000s 14027.911us 1 1 100.00
entropy_src_fw_ov 93.000s 13329.615us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 93.000s 13329.615us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 264.000s 14027.911us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 330.000s 14110.975us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 264.000s 14027.911us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 264.000s 14027.911us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 264.000s 14027.911us 1 1 100.00
entropy_src_intr 42.000s 990.672us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 264.000s 14027.911us 1 1 100.00
entropy_src_functional_alerts 10.000s 698.390us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 519.000s 14248.268us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 3.000s 56.533us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 4.000s 734.499us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 2.000s 88.573us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 16.907us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 7.000s 613.509us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 7.000s 613.509us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 31.268us 1 1 100.00
entropy_src_csr_rw 2.000s 18.379us 1 1 100.00
entropy_src_csr_aliasing 3.000s 45.717us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 64.531us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 31.268us 1 1 100.00
entropy_src_csr_rw 2.000s 18.379us 1 1 100.00
entropy_src_csr_aliasing 3.000s 45.717us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 64.531us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 5.000s 146.972us 1 1 100.00
entropy_src_tl_intg_err 6.000s 889.018us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 264.000s 14027.911us 1 1 100.00
entropy_src_cfg_regwen 3.000s 39.447us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 264.000s 14027.911us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 264.000s 14027.911us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 264.000s 14027.911us 1 1 100.00
entropy_src_fw_ov 93.000s 13329.615us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 3.000s 56.533us 1 1 100.00
entropy_src_sec_cm 5.000s 146.972us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 3.000s 56.533us 1 1 100.00
entropy_src_sec_cm 5.000s 146.972us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 264.000s 14027.911us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 3.000s 56.533us 1 1 100.00
entropy_src_sec_cm 5.000s 146.972us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 3.000s 56.533us 1 1 100.00
entropy_src_sec_cm 5.000s 146.972us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 3.000s 56.533us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 10.000s 698.390us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 6.000s 889.018us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 114.000s 14182.672us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 3.000s 17.235us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1661) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.extht_lo_threshold 1 test run
entropy_src_stress_all_with_rand_reset 92718072235910359118583782820463590162736619480400365996640209238283196156872 116
UVM_INFO @ 17235318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---