| V1 |
|
77.78% |
| V2 |
|
82.35% |
| V2S |
|
100.00% |
| V3 |
|
50.00% |
| unmapped |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 4 | 4 | 100.00 | |||
| gpio_smoke | 1.860s | 155.516us | 1 | 1 | 100.00 | |
| gpio_smoke_no_pullup_pulldown | 2.250s | 190.260us | 1 | 1 | 100.00 | |
| gpio_smoke_en_cdc_prim | 1.420s | 73.739us | 1 | 1 | 100.00 | |
| gpio_smoke_no_pullup_pulldown_en_cdc_prim | 1.430s | 78.002us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| gpio_csr_hw_reset | 1.020s | 24.724us | 1 | 1 | 100.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| gpio_csr_rw | 1.030s | 13.609us | 0 | 1 | 0.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| gpio_csr_bit_bash | 10.730s | 1094.540us | 1 | 1 | 100.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| gpio_csr_aliasing | 1.190s | 8.039us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| gpio_csr_mem_rw_with_rand_reset | 1.270s | 127.813us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| gpio_csr_rw | 1.030s | 13.609us | 0 | 1 | 0.00 | |
| gpio_csr_aliasing | 1.190s | 8.039us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| direct_and_masked_out | 2 | 2 | 100.00 | |||
| gpio_random_dout_din | 1.910s | 36.975us | 1 | 1 | 100.00 | |
| gpio_random_dout_din_no_pullup_pulldown | 1.200s | 58.218us | 1 | 1 | 100.00 | |
| out_in_regs_read_write | 1 | 1 | 100.00 | |||
| gpio_dout_din_regs_random_rw | 0.900s | 96.606us | 1 | 1 | 100.00 | |
| gpio_interrupt_programming | 1 | 1 | 100.00 | |||
| gpio_intr_rand_pgm | 1.730s | 194.441us | 1 | 1 | 100.00 | |
| random_interrupt_trigger | 1 | 1 | 100.00 | |||
| gpio_rand_intr_trigger | 3.470s | 198.998us | 1 | 1 | 100.00 | |
| interrupt_and_noise_filter | 1 | 1 | 100.00 | |||
| gpio_intr_with_filter_rand_intr_event | 4.530s | 91.927us | 1 | 1 | 100.00 | |
| noise_filter_stress | 1 | 1 | 100.00 | |||
| gpio_filter_stress | 14.060s | 1928.850us | 1 | 1 | 100.00 | |
| regs_long_reads_and_writes | 1 | 1 | 100.00 | |||
| gpio_random_long_reg_writes_reg_reads | 10.270s | 641.042us | 1 | 1 | 100.00 | |
| full_random | 1 | 1 | 100.00 | |||
| gpio_full_random | 1.280s | 59.140us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| gpio_stress_all | 109.400s | 81507.285us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| gpio_alert_test | 0.820s | 17.114us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| gpio_intr_test | 0.890s | 125.959us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| gpio_tl_errors | 2.300s | 174.500us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| gpio_tl_errors | 2.300s | 174.500us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 1 | 4 | 25.00 | |||
| gpio_csr_rw | 1.030s | 13.609us | 0 | 1 | 0.00 | |
| gpio_same_csr_outstanding | 1.220s | 23.099us | 0 | 1 | 0.00 | |
| gpio_csr_aliasing | 1.190s | 8.039us | 0 | 1 | 0.00 | |
| gpio_csr_hw_reset | 1.020s | 24.724us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 1 | 4 | 25.00 | |||
| gpio_csr_rw | 1.030s | 13.609us | 0 | 1 | 0.00 | |
| gpio_same_csr_outstanding | 1.220s | 23.099us | 0 | 1 | 0.00 | |
| gpio_csr_aliasing | 1.190s | 8.039us | 0 | 1 | 0.00 | |
| gpio_csr_hw_reset | 1.020s | 24.724us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| gpio_tl_intg_err | 2.340s | 85.026us | 1 | 1 | 100.00 | |
| gpio_sec_cm | 1.270s | 398.274us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| gpio_tl_intg_err | 2.340s | 85.026us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| straps_data | 1 | 1 | 100.00 | |||
| gpio_rand_straps | 0.890s | 24.427us | 1 | 1 | 100.00 | |
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| gpio_stress_all_with_rand_reset | 2.220s | 66.309us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 1 | 1 | 100.00 | |||
| gpio_inp_prd_cnt | 0.920s | 14.442us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: gpio_reg_block.inp_prd_cnt_val_* reset value: * | 2 test runs | |||
| gpio_csr_rw | 93823870760657289881582462476805117434416404776143317971498374497106358188122 | 84 |
UVM_INFO @ 13608963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_csr_aliasing | 31705514455150315330922511009386847145222912057653942416368162879430027978302 | 96 |
UVM_INFO @ 8039449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:1230) [gpio_common_vseq] Check failed (vseq_done) | 1 test run | |||
| gpio_stress_all_with_rand_reset | 97514782914811561237314864659592063649827389518539467636641809840432519893497 | 86 |
UVM_INFO @ 66308998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:660) [gpio_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch | 1 test run | |||
| gpio_same_csr_outstanding | 57540028472708413334940874928230374431300889056665109360899608943724574783478 | 83 |
UVM_INFO @ 23099383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|