Simulation Results: hmac

 
08/09/2026 15:31:51 DVSim: v1.52.1 sha: 82334bf json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 69.62 %
  • code
  • 83.19 %
  • assert
  • 97.17 %
  • func
  • 28.49 %
  • block
  • 97.46 %
  • line
  • 98.39 %
  • branch
  • 93.64 %
  • toggle
  • 45.89 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 21.000s 1607.846us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.000s 28.285us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 1.000s 22.071us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 16.000s 1352.056us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.000s 148.882us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 4.000s 34.107us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 1.000s 22.071us 1 1 100.00
hmac_csr_aliasing 2.000s 148.882us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 68.000s 7111.449us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 122.000s 42208.209us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 281.000s 35518.261us 1 1 100.00
hmac_test_sha384_vectors 38.000s 340.030us 1 1 100.00
hmac_test_sha512_vectors 36.000s 1396.331us 1 1 100.00
hmac_test_hmac256_vectors 10.000s 210.968us 1 1 100.00
hmac_test_hmac384_vectors 20.000s 929.106us 1 1 100.00
hmac_test_hmac512_vectors 26.000s 535.633us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 13.000s 216.258us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 282.000s 22291.079us 1 1 100.00
error 1 1 100.00
hmac_error 80.000s 9882.637us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 103.000s 3350.842us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 21.000s 1607.846us 1 1 100.00
hmac_long_msg 68.000s 7111.449us 1 1 100.00
hmac_back_pressure 122.000s 42208.209us 1 1 100.00
hmac_datapath_stress 282.000s 22291.079us 1 1 100.00
hmac_burst_wr 13.000s 216.258us 1 1 100.00
hmac_stress_all 372.000s 134684.971us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 21.000s 1607.846us 1 1 100.00
hmac_long_msg 68.000s 7111.449us 1 1 100.00
hmac_back_pressure 122.000s 42208.209us 1 1 100.00
hmac_datapath_stress 282.000s 22291.079us 1 1 100.00
hmac_wipe_secret 103.000s 3350.842us 1 1 100.00
hmac_test_sha256_vectors 281.000s 35518.261us 1 1 100.00
hmac_test_sha384_vectors 38.000s 340.030us 1 1 100.00
hmac_test_sha512_vectors 36.000s 1396.331us 1 1 100.00
hmac_test_hmac256_vectors 10.000s 210.968us 1 1 100.00
hmac_test_hmac384_vectors 20.000s 929.106us 1 1 100.00
hmac_test_hmac512_vectors 26.000s 535.633us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 21.000s 1607.846us 1 1 100.00
hmac_long_msg 68.000s 7111.449us 1 1 100.00
hmac_back_pressure 122.000s 42208.209us 1 1 100.00
hmac_datapath_stress 282.000s 22291.079us 1 1 100.00
hmac_burst_wr 13.000s 216.258us 1 1 100.00
hmac_error 80.000s 9882.637us 1 1 100.00
hmac_wipe_secret 103.000s 3350.842us 1 1 100.00
hmac_test_sha256_vectors 281.000s 35518.261us 1 1 100.00
hmac_test_sha384_vectors 38.000s 340.030us 1 1 100.00
hmac_test_sha512_vectors 36.000s 1396.331us 1 1 100.00
hmac_test_hmac256_vectors 10.000s 210.968us 1 1 100.00
hmac_test_hmac384_vectors 20.000s 929.106us 1 1 100.00
hmac_test_hmac512_vectors 26.000s 535.633us 1 1 100.00
hmac_stress_all 372.000s 134684.971us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 372.000s 134684.971us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 1.000s 138.467us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 1.000s 13.489us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.000s 240.756us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.000s 240.756us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.000s 28.285us 1 1 100.00
hmac_csr_rw 1.000s 22.071us 1 1 100.00
hmac_csr_aliasing 2.000s 148.882us 1 1 100.00
hmac_same_csr_outstanding 2.000s 82.442us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.000s 28.285us 1 1 100.00
hmac_csr_rw 1.000s 22.071us 1 1 100.00
hmac_csr_aliasing 2.000s 148.882us 1 1 100.00
hmac_same_csr_outstanding 2.000s 82.442us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 2.000s 64.518us 1 1 100.00
hmac_tl_intg_err 3.000s 110.435us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.000s 110.435us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 21.000s 1607.846us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 5.000s 1411.597us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 140.000s 19473.681us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 3.000s 35.351us 1 1 100.00