Simulation Results

Simulation Results: i2c

08/09/2026 15:31:51 DVSim: v1.52.1 sha: 82334bf json Branch: master Tool: xcelium [24.03-s007]

Coverage statistics

Total
88.99 %

code
86.48 %

assert
97.46 %

func
83.03 %

block
96.30 %

line
95.70 %

branch
93.39 %

toggle
72.68 %

FSM
84.17 %

Validation stages

V1		100.00%
V2		87.80%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	25.000s	4959.807us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	10.000s	2231.759us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	1.000s	23.028us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	1.000s	72.492us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	5.000s	290.670us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.000s	91.879us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.000s	110.615us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	1.000s	72.492us	1	1	100.00
	i2c_csr_aliasing	1.000s	91.879us	1	1	100.00

36/41 passed

87.80 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	2.000s	13.365us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	48.000s	2240.680us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	11.000s	3433.530us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	2.000s	141.681us	1	1	100.00
host_fifo_watermark				0	1	0.00
	i2c_host_fifo_watermark	3600.000s	0.000us	0	1	0.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	1783.000s	13409.856us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	2.000s	404.549us	1	1	100.00
	i2c_host_fifo_fmt_empty	14.000s	3544.862us	1	1	100.00
	i2c_host_fifo_reset_rx	4.000s	125.347us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	1746.000s	3160.336us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	12.000s	1016.924us	1	1	100.00
i2c_host_mode_toggle				1	1	100.00
	i2c_host_mode_toggle	5.000s	107.099us	1	1	100.00
target_glitch				0	1	0.00
	i2c_target_glitch	6.000s	536.735us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	2271.000s	28878.949us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	8.000s	2932.796us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	60.000s	5769.974us	1	1	100.00
	i2c_target_intr_smoke	10.000s	4764.996us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	2.000s	257.499us	1	1	100.00
	i2c_target_fifo_reset_tx	3.000s	2777.170us	1	1	100.00
target_fifo_full				2	3	66.67
	i2c_target_stress_wr	3600.000s	0.000us	0	1	0.00
	i2c_target_stress_rd	60.000s	5769.974us	1	1	100.00
	i2c_target_intr_stress_wr	14.000s	3302.552us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	12.000s	6686.765us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	13.000s	1537.778us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	10.000s	1560.937us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	2.000s	1661.040us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	5.000s	1806.421us	1	1	100.00
	i2c_target_fifo_watermarks_tx	2.000s	103.389us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	11.000s	3433.530us	1	1	100.00
	i2c_host_perf_precise	8.000s	231.738us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	12.000s	1016.924us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	7.000s	393.494us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	5.000s	2048.799us	1	1	100.00
	i2c_target_nack_acqfull_addr	4.000s	1091.764us	1	1	100.00
	i2c_target_nack_txstretch	3.000s	238.675us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	11.000s	1779.174us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	4.000s	1542.179us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	1.000s	17.385us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	2.000s	47.326us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	3.000s	170.299us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	3.000s	170.299us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	1.000s	23.028us	1	1	100.00
	i2c_csr_rw	1.000s	72.492us	1	1	100.00
	i2c_csr_aliasing	1.000s	91.879us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	87.296us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	1.000s	23.028us	1	1	100.00
	i2c_csr_rw	1.000s	72.492us	1	1	100.00
	i2c_csr_aliasing	1.000s	91.879us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	87.296us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	3.000s	148.433us	1	1	100.00
	i2c_sec_cm	2.000s	258.244us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	3.000s	148.433us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	21.000s	938.259us	1
target_error_intr				1
	i2c_target_unexp_stop	3.000s	182.629us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	20.000s	1133.755us	1

Error Messages

	Test	seed	line	log context
Job timed out after * minutes				2 test runs
	i2c_host_fifo_watermark	27196927833575225547939664488834526166432824422874191562725621119329374860222	None
	i2c_target_stress_wr	32347464543604809736440820779215230443438251457239597300884026617070731856197	None
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				2 test runs
	i2c_host_error_intr	86310558110551648492754589911512576929678380727987656805191655986347176535020	89	UVM_INFO @ 13364861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	62636452797403783496627055633901278664716858594424140022735439443801138996749	110	UVM_INFO @ 2240679581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1297) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	i2c_host_stress_all_with_rand_reset	112694272931287922393018912766911640868231235817297395555509324174763824334639	97	UVM_INFO @ 938259495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	43054985961214174980379079266126046683407708135958365634856194133697517608529	100	UVM_INFO @ 1133755145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	57078059549915399339367307475460729654820084999195580003877007732918367346199	93	UVM_INFO @ 536734615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:680) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	17815681925085876375560912160783431801569889064459727294871563678769626102489	87	UVM_INFO @ 182629476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---