Simulation Results: lc_ctrl/volatile_unlock_disabled

 
08/09/2026 15:31:51 DVSim: v1.52.1 sha: 82334bf json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 88.71 %
  • code
  • 91.44 %
  • assert
  • 95.97 %
  • func
  • 78.71 %
  • block
  • 96.12 %
  • line
  • 97.05 %
  • branch
  • 90.11 %
  • toggle
  • 83.35 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
73.33%
V2S
60.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 78.056us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 32.351us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 19.769us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 3.000s 128.876us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 17.401us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.000s 94.006us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 19.769us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 17.401us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 300.952us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 20.606us 1 1 100.00
lc_prog_failure 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_errors 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
security_escalation 2 7 28.57
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_security_escalation 6.000s 416.936us 1 1 100.00
lc_ctrl_jtag_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3.000s 241.829us 0 1 0.00
lc_ctrl_jtag_errors 23.000s 8916.221us 1 1 100.00
jtag_access 11 13 84.62
lc_ctrl_jtag_smoke 3.000s 229.964us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3.000s 63.967us 0 1 0.00
lc_ctrl_jtag_prog_failure 3.000s 241.829us 0 1 0.00
lc_ctrl_jtag_errors 23.000s 8916.221us 1 1 100.00
lc_ctrl_jtag_access 13.000s 2499.837us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 7.000s 821.374us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 82.445us 1 1 100.00
lc_ctrl_jtag_csr_rw 3.000s 516.251us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 9.000s 2785.446us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.000s 148.100us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 104.129us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.000s 955.072us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 241.626us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 7.000s 1735.122us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.000s 11.950us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 10804.448s 0.000us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.000s 62.545us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 4.000s 45.534us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 4.000s 45.534us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 32.351us 1 1 100.00
lc_ctrl_csr_rw 1.000s 19.769us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 17.401us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 30.986us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 32.351us 1 1 100.00
lc_ctrl_csr_rw 1.000s 19.769us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 17.401us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 30.986us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 4.000s 477.142us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 69.879us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 69.879us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 300.952us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 477.142us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 477.142us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 477.142us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 477.142us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 477.142us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 477.142us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 477.142us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 477.142us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.000s 416.936us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_state_post_trans 3.000s 63.967us 0 1 0.00
sec_cm_intersig_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.000s 264.865us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 8.000s 504.708us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 8.000s 504.708us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3601.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 8 test runs
lc_ctrl_state_failure 88150797004137138655081797963673440028196622602821030752669077400935170090924 None
lc_ctrl_state_post_trans 63882003414210247652645186021441422654834294222072707055929369356371808334765 None
lc_ctrl_prog_failure 71019727673929398793438586171332485988489225053661417048871023083882764365847 None
lc_ctrl_errors 77927084055086661100014779738164047966906889794574009596879425373522378519436 None
lc_ctrl_jtag_state_failure 110861894542187434208573399109493509592821872782095370386516154282374310002938 None
lc_ctrl_sec_mubi 108758195379392304145210343893925409652204545485136645041537374415334014493438 None
lc_ctrl_stress_all 12332921022829499562501075998943762479330110978253358720072655416609990400606 None
lc_ctrl_stress_all_with_rand_reset 82820306537459738020644342325837268294265229443479885049327607475410600781260 None
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 1 test run
lc_ctrl_jtag_state_post_trans 36070377943055369211715936288103108410596501495144673366568873968872160954667 179
UVM_INFO @ 63967338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_prog_error has unexpected timeout error 1 test run
lc_ctrl_jtag_prog_failure 68464988546936642579373421853532333611733709685314664418059080314987075252549 194
UVM_INFO @ 241828855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---