Simulation Results: lc_ctrl/volatile_unlock_enabled

 
08/09/2026 15:31:51 DVSim: v1.52.1 sha: 82334bf json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 89.14 %
  • code
  • 90.87 %
  • assert
  • 96.54 %
  • func
  • 80.00 %
  • block
  • 96.57 %
  • line
  • 97.39 %
  • branch
  • 91.30 %
  • toggle
  • 79.55 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
76.67%
V2S
70.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 15.698us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 25.162us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 35.874us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 3.000s 118.365us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 36.450us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 61.115us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 35.874us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 36.450us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.000s 340.460us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 7.000s 1130.011us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 70.448us 1 1 100.00
lc_prog_failure 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.000s 1000.636us 1 1 100.00
security_escalation 2 7 28.57
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_errors 6.000s 1000.636us 1 1 100.00
lc_ctrl_security_escalation 6.000s 1125.250us 1 1 100.00
lc_ctrl_jtag_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3600.000s 0.000us 0 1 0.00
jtag_access 10 13 76.92
lc_ctrl_jtag_smoke 6.000s 4537.367us 1 1 100.00
lc_ctrl_jtag_state_post_trans 2.000s 50.267us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_access 7.000s 541.632us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 10.000s 1004.788us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 107.833us 1 1 100.00
lc_ctrl_jtag_csr_rw 3.000s 1045.265us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 11.000s 1055.484us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.000s 714.150us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 224.519us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 59.633us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 55.449us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.000s 190.762us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 18.788us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 10802.115s 0.000us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 15.995us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 157.542us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 157.542us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 25.162us 1 1 100.00
lc_ctrl_csr_rw 1.000s 35.874us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 36.450us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.000s 118.068us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 25.162us 1 1 100.00
lc_ctrl_csr_rw 1.000s 35.874us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 36.450us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.000s 118.068us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 489.179us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 81.424us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 81.424us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 7.000s 1130.011us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 489.179us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 489.179us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 489.179us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 489.179us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 489.179us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 489.179us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 489.179us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 489.179us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.000s 1125.250us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 1 2 50.00
lc_ctrl_state_post_trans 3.000s 340.460us 1 1 100.00
lc_ctrl_jtag_state_post_trans 2.000s 50.267us 0 1 0.00
sec_cm_intersig_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 9.000s 474.576us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 3702.813us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 3702.813us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3600.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 8 test runs
lc_ctrl_state_failure 72779345916773075000035450705884107621994996060256191750401920321667428276124 None
lc_ctrl_prog_failure 6246694441536644723878081510493027134361757688524209125587877873369836924161 None
lc_ctrl_jtag_state_failure 47982979068478650772252642411105514926400515186561398010583743100492820362634 None
lc_ctrl_jtag_prog_failure 108523546366647802071327930068247120850104517925341455963558483528238162579129 None
lc_ctrl_jtag_errors 42470806547589667803477947963890688266482374007634926905404072537061841350277 None
lc_ctrl_sec_mubi 33510266028344491942302799633263468059302714738248527325878353641811543162727 None
lc_ctrl_stress_all 84020410678500286727548557818989532620062669477239761312942599065660747794121 None
lc_ctrl_stress_all_with_rand_reset 73997398984638754147555138875187697260567560576979785978901743370978717017288 None
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 1 test run
lc_ctrl_jtag_state_post_trans 76628413199608296622000730148718581421906282799556914268630983497241809731771 175
UVM_INFO @ 50267228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---