Simulation Results: rom_ctrl/64kb

 
08/09/2026 15:31:51 DVSim: v1.52.1 sha: 82334bf json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.57 %
  • code
  • 79.93 %
  • assert
  • 97.38 %
  • func
  • 97.39 %
  • block
  • 78.65 %
  • line
  • 79.01 %
  • branch
  • 79.77 %
  • toggle
  • 84.74 %
  • FSM
  • 76.19 %
Validation stages
V1
100.00%
V2
77.78%
V2S
66.67%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 5.000s 2047.927us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 3.000s 55.349us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.000s 58.165us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.000s 173.959us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 65.057us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.000s 58.765us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.000s 58.165us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 65.057us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 2.000s 61.320us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 2.000s 56.942us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 5.000s 1315.245us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 7.000s 169.889us 1 1 100.00
kmac_err_chk 0 1 0.00
rom_ctrl_kmac_err_chk 3601.000s 0.000us 0 1 0.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.000s 70.819us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 5.000s 121.077us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 5.000s 121.077us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.000s 55.349us 1 1 100.00
rom_ctrl_csr_rw 3.000s 58.165us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 65.057us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 131.440us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.000s 55.349us 1 1 100.00
rom_ctrl_csr_rw 3.000s 58.165us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 65.057us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 131.440us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 8.000s 273.190us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 281.000s 854.422us 1 1 100.00
rom_ctrl_tl_intg_err 57.000s 239.014us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 281.000s 854.422us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 281.000s 854.422us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 281.000s 854.422us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 281.000s 854.422us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 5.000s 2047.927us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 5.000s 2047.927us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 5.000s 2047.927us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 57.000s 239.014us 1 1 100.00
sec_cm_bus_local_esc 0 2 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
rom_ctrl_kmac_err_chk 3601.000s 0.000us 0 1 0.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 8.000s 273.190us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 281.000s 854.422us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 21.000s 6303.592us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
rom_ctrl_corrupt_sig_fatal_chk 88598171781313614041063328041908864962286695241809314539159091634617404111865 None
rom_ctrl_kmac_err_chk 60923855469158508819482668702485422252776282001733307840342654867288653126154 None
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 19405312667647660660937896486035188937538004575799629432451862350764551171564 88
UVM_INFO @ 1315244769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---