Simulation Results: rstmgr

 
08/09/2026 15:31:51 DVSim: v1.52.1 sha: 82334bf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.24 %
  • code
  • 99.37 %
  • assert
  • 98.35 %
  • func
  • 96.99 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.86 %
  • toggle
  • 99.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.680s 74.775us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.280s 94.648us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 1.250s 39.404us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 2.780s 59.400us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.410s 37.281us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 2.180s 97.403us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 1.250s 39.404us 1 1 100.00
rstmgr_csr_aliasing 1.410s 37.281us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.770s 115.647us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.570s 47.892us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.550s 69.746us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 7.640s 598.648us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 7.640s 598.648us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 7.640s 598.648us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 7.640s 598.648us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 25.890s 3009.357us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.350s 48.775us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.940s 40.117us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.940s 40.117us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.280s 94.648us 1 1 100.00
rstmgr_csr_rw 1.250s 39.404us 1 1 100.00
rstmgr_csr_aliasing 1.410s 37.281us 1 1 100.00
rstmgr_same_csr_outstanding 1.540s 42.368us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.280s 94.648us 1 1 100.00
rstmgr_csr_rw 1.250s 39.404us 1 1 100.00
rstmgr_csr_aliasing 1.410s 37.281us 1 1 100.00
rstmgr_same_csr_outstanding 1.540s 42.368us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 48.630s 6798.582us 1 1 100.00
rstmgr_tl_intg_err 6.920s 615.124us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 48.630s 6798.582us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 48.630s 6798.582us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 6.920s 615.124us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.640s 67.264us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 5.310s 423.834us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 3.280s 292.416us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 48.630s 6798.582us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 1.250s 39.404us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 1.250s 39.404us 1 1 100.00