Simulation Results

Simulation Results: rv_dm/use_dmi_interface

08/09/2026 15:31:51 DVSim: v1.52.1 sha: 82334bf json Branch: master Tool: xcelium [24.03-s007]

Coverage statistics

Total
87.72 %

code
73.48 %

assert
96.59 %

func
93.08 %

block
89.52 %

line
89.42 %

branch
71.56 %

toggle
72.25 %

FSM
60.71 %

Validation stages

V1		92.59%
V2		69.57%
V2S		85.71%
V3		0.00%
unmapped		0.00%

25/27 passed

92.59 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	53.000s	1348.549us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	45.000s	221.613us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	41.000s	420.353us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	55.000s	10609.021us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	44.000s	1145.240us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	46.000s	4102.645us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	47.000s	4562.864us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	40.000s	38.484us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	49.000s	4830.814us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	46.000s	909.311us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	44.000s	505.803us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	43.000s	200.079us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	42.000s	181.336us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	43.000s	133.688us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	42.000s	522.303us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	45.000s	192.521us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	42.000s	256.431us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	46.000s	909.311us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	46.000s	179.130us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	46.000s	208.217us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	43.000s	200.079us	1	1	100.00
rom_read_access				0	1	0.00
	rv_dm_rom_read_access	39.000s	28.152us	0	1	0.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	44.000s	832.946us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	45.000s	133.983us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	100.000s	16734.536us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	45.000s	217.757us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	45.000s	110.516us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	45.000s	217.757us	1	1	100.00
	rv_dm_csr_rw	45.000s	133.983us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	43.000s	41.781us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	42.000s	41.075us	1	1	100.00

16/23 passed

69.57 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	53.000s	1348.549us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	46.000s	421.649us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	44.000s	329.663us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	42.000s	196.421us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	39.000s	1115.431us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	35.000s	980.839us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	42.000s	186.955us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	48.000s	2567.702us	0	1	0.00
sba_autoincrement				0	1	0.00
	rv_dm_autoincr_sba_tl_access	44.000s	50.217us	0	1	0.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	41.000s	343.771us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	52.000s	4684.912us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	40.000s	165.483us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	43.000s	107.721us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm	70.000s	13373.689us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	71.000s	4358.237us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	42.000s	107.405us	1	1	100.00
stress_all				0	1	0.00
	rv_dm_stress_all	47.000s	2785.431us	0	1	0.00
alert_test				1	1	100.00
	rv_dm_alert_test	43.000s	100.281us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	49.000s	364.361us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	49.000s	364.361us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	45.000s	217.757us	1	1	100.00
	rv_dm_csr_hw_reset	44.000s	832.946us	1	1	100.00
	rv_dm_csr_rw	45.000s	133.983us	1	1	100.00
	rv_dm_same_csr_outstanding	45.000s	508.311us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	45.000s	217.757us	1	1	100.00
	rv_dm_csr_hw_reset	44.000s	832.946us	1	1	100.00
	rv_dm_csr_rw	45.000s	133.983us	1	1	100.00
	rv_dm_same_csr_outstanding	45.000s	508.311us	1	1	100.00

V2S

6/7 passed

85.71 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_sec_cm	35.000s	388.455us	1	1	100.00
	rv_dm_tl_intg_err	43.000s	4905.929us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	43.000s	4905.929us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	52.000s	4684.912us	1	1	100.00
	rv_dm_debug_disabled	39.000s	151.301us	1	1	100.00
sec_cm_lc_dft_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	52.000s	4684.912us	1	1	100.00
	rv_dm_debug_disabled	39.000s	151.301us	1	1	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	53.000s	1348.549us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				0	1	0.00
	rv_dm_buffered_enable	41.000s	160.157us	0	1	0.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	36.000s	63.528us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	36.000s	63.528us	1	1	100.00
sec_cm_exec_ctrl_mubi				0	1	0.00
	rv_dm_buffered_enable	41.000s	160.157us	0	1	0.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	rv_dm_stress_all_with_rand_reset	47.000s	316.519us	0	1	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	194.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				3 test runs
	rv_dm_delayed_resp_sba_tl_access	13216980982887346938604519114190243558730469664423158808302648395948276038354	107	UVM_INFO @ 186954749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	75749436106748942721930792427674427764847340493210791068826253940318350222905	128	UVM_INFO @ 2567701509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	44417566357440445400941899412800857979853142744065695438456700431376612977163	107	UVM_INFO @ 50217100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				2 test runs
	rv_dm_mem_tl_access_resuming	53527134797261034711817842734845022065775101939968705311265107770146658390116	87	UVM_INFO @ 181335680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	114161621209369344145083536547356790000703160947755157534011481876847232786169	89	UVM_INFO @ 2785431253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				2 test runs
	rv_dm_hart_unavail	56713832372026050265721118689222863152929930388733334731130930010877053905114	87	UVM_INFO @ 107721062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	58841529916613383755944999772025307702984328705589433776212442326270818497726	93	UVM_INFO @ 316519255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:481) [scoreboard] sba_tl_access_q item uncompared:				1 test run
	rv_dm_sba_tl_access	71986485226656321335467061978201903462084730699013274205915294679683061488637	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23857
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				1 test run
	rv_dm_jtag_dmi_debug_disabled	4190989292320178903817601433171788031270361370947831118693988832657074803672	87	UVM_INFO @ 343770524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:409) scoreboard [scoreboard] Unexpected response to read from address * in mem reg block. Problems: '{"Expected read d_data=, but it was "}. Item: (req: (cip_tl_seq_item@23888) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }				1 test run
	rv_dm_rom_read_access	55481352913364161849174501591519531492076288425723886194016923853253100988764	87	). UVM_INFO @ 28152493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_buffered_enable_vseq.sv:164) [rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (* [] vs [*])				1 test run
	rv_dm_buffered_enable	103146549545354560018824508743718439863531668874118131152781755020159770547787	89	UVM_INFO @ 160157026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				1 test run
	rv_dm_scanmode	34259400520384128844174202493226058361644266106935789577097736397323395317404	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---