Simulation Results: spi_device/1r1w

 
08/09/2026 15:31:51 DVSim: v1.52.1 sha: 82334bf json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 85.64 %
  • code
  • 89.48 %
  • assert
  • 95.40 %
  • func
  • 72.04 %
  • block
  • 98.34 %
  • line
  • 98.61 %
  • branch
  • 96.99 %
  • toggle
  • 72.75 %
  • FSM
  • 89.58 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 268.000s 10301.651us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 2.000s 48.705us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 4.000s 438.026us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 27.000s 1136.229us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 3.000s 47.467us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 6.000s 159.113us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 4.000s 438.026us 1 1 100.00
spi_device_csr_aliasing 3.000s 47.467us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 2.000s 34.267us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 2.000s 35.983us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 2.000s 39.190us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 2.000s 5.695us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 2.000s 3.282us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 2.000s 54.067us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 2.000s 54.067us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 42.000s 4057.215us 1 1 100.00
spi_device_tpm_sts_read 3.000s 178.525us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 80.000s 14233.583us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 9.000s 426.467us 1 1 100.00
spi_device_flash_all 242.000s 16311.567us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 7.000s 767.569us 1 1 100.00
spi_device_flash_all 242.000s 16311.567us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 7.000s 767.569us 1 1 100.00
spi_device_flash_all 242.000s 16311.567us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 242.000s 16311.567us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 8.000s 132.068us 1 1 100.00
spi_device_flash_all 242.000s 16311.567us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 8.000s 132.068us 1 1 100.00
spi_device_flash_all 242.000s 16311.567us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 8.000s 132.068us 1 1 100.00
spi_device_flash_all 242.000s 16311.567us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 8.000s 132.068us 1 1 100.00
spi_device_flash_all 242.000s 16311.567us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 8.000s 132.068us 1 1 100.00
spi_device_flash_all 242.000s 16311.567us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 49.000s 11855.828us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 240.000s 14096.585us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 240.000s 14096.585us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 240.000s 14096.585us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 7.000s 432.606us 1 1 100.00
spi_device_read_buffer_direct 4.000s 98.026us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 240.000s 14096.585us 1 1 100.00
spi_device_flash_all 242.000s 16311.567us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 242.000s 16311.567us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 242.000s 16311.567us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 15.000s 5276.233us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 15.000s 5276.233us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 57.000s 13473.985us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 268.000s 10301.651us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 540.000s 68788.495us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 281.000s 85202.277us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 2.000s 22.695us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 2.000s 115.177us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 6.000s 145.377us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 6.000s 145.377us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 48.705us 1 1 100.00
spi_device_csr_rw 4.000s 438.026us 1 1 100.00
spi_device_csr_aliasing 3.000s 47.467us 1 1 100.00
spi_device_same_csr_outstanding 2.000s 28.336us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 48.705us 1 1 100.00
spi_device_csr_rw 4.000s 438.026us 1 1 100.00
spi_device_csr_aliasing 3.000s 47.467us 1 1 100.00
spi_device_same_csr_outstanding 2.000s 28.336us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 2.000s 81.627us 1 1 100.00
spi_device_tl_intg_err 24.000s 2477.522us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 24.000s 2477.522us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
spi_device_mem_parity 34908254475904688449720595229299050867076426273019143842251303258676742282615 87
UVM_ERROR @ 4139746 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
ERROR: VHPI NOTFOUND
Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[939] not found within the scope .
UVM_ERROR @ 4139746 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[939] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 72880278303284689267186787707040261834625148168001368321944465138472398141237 85
UVM_ERROR @ 1090463 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe2 [11100010] vs 0x0 [0])
UVM_ERROR @ 1112463 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x171 [101110001] vs 0x0 [0])
UVM_ERROR @ 1198463 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x280 [1010000000] vs 0x0 [0])
UVM_ERROR @ 1260463 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2a4 [1010100100] vs 0x0 [0])