Simulation Results: sram_ctrl/main

 
08/09/2026 15:31:51 DVSim: v1.52.1 sha: 82334bf json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 95.42 %
  • code
  • 94.83 %
  • assert
  • 97.83 %
  • func
  • 93.60 %
  • block
  • 94.14 %
  • line
  • 95.27 %
  • branch
  • 92.21 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 4.000s 2786.935us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 42.317us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 22.161us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 36.168us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 22.976us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 369.038us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 22.161us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 22.976us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 357.000s 92693.430us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 70.000s 1369.460us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 50.000s 77827.433us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 168.000s 3534.389us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 249.000s 72806.860us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 48.000s 12962.844us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 14.000s 3288.798us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 29.000s 4473.399us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 7.000s 724.513us 1 1 100.00
sram_ctrl_partial_access_b2b 219.000s 48605.892us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 6.000s 7388.939us 1 1 100.00
sram_ctrl_throughput_w_partial_write 7.000s 5109.922us 1 1 100.00
sram_ctrl_throughput_w_readback 7.000s 3350.072us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 11.000s 2167.205us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 350.920us 1 1 100.00
non_pow2_mem_size 3 3 100.00
sram_ctrl_smoke 4.000s 2786.935us 1 1 100.00
sram_ctrl_partial_access 7.000s 724.513us 1 1 100.00
sram_ctrl_access_during_key_req 48.000s 12962.844us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 311.000s 34579.113us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 27.808us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 5.000s 141.300us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 5.000s 141.300us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 42.317us 1 1 100.00
sram_ctrl_csr_rw 2.000s 22.161us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 22.976us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 27.083us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 42.317us 1 1 100.00
sram_ctrl_csr_rw 2.000s 22.161us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 22.976us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 27.083us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 30.000s 13904.149us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 493.493us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 399.841us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 493.493us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 399.841us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 11.000s 2167.205us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 11.000s 2167.205us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 22.161us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 29.000s 4473.399us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 29.000s 4473.399us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 29.000s 4473.399us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 14.000s 3288.798us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 30.000s 13904.149us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 2786.935us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 2786.935us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 29.000s 4473.399us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 493.493us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 14.000s 3288.798us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 493.493us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 493.493us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 4.000s 2786.935us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 493.493us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 29.000s 3469.494us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 75332667150500088745168599169869522166512575053747869889101471734302514908140 None
sram_ctrl_mubi_enc_err 132285283590286653790428438352545189069261020275699944893686267506343595821 None