Simulation Results: sram_ctrl/ret

 
08/09/2026 15:31:51 DVSim: v1.52.1 sha: 82334bf json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.06 %
  • code
  • 81.71 %
  • assert
  • 97.26 %
  • func
  • 94.20 %
  • block
  • 92.12 %
  • line
  • 93.78 %
  • branch
  • 88.07 %
  • toggle
  • 78.32 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 97.080us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 39.161us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 47.315us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 431.089us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 15.401us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 72.435us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 47.315us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 15.401us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 6.000s 394.618us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 7.000s 234.573us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 21.000s 1484.987us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 171.000s 2810.345us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 7.000s 572.144us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 18.000s 1001.420us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 7.000s 2627.128us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 13.000s 465.388us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 64.170us 1 1 100.00
sram_ctrl_partial_access_b2b 417.000s 22121.832us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 1.000s 131.262us 1 1 100.00
sram_ctrl_throughput_w_partial_write 2.000s 36.147us 1 1 100.00
sram_ctrl_throughput_w_readback 2.000s 140.056us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 5.000s 973.430us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 33.209us 1 1 100.00
non_pow2_mem_size 3 3 100.00
sram_ctrl_smoke 2.000s 97.080us 1 1 100.00
sram_ctrl_partial_access 2.000s 64.170us 1 1 100.00
sram_ctrl_access_during_key_req 18.000s 1001.420us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 49.000s 12130.559us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 59.483us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 10.000s 43.239us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 10.000s 43.239us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 39.161us 1 1 100.00
sram_ctrl_csr_rw 2.000s 47.315us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 15.401us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 40.184us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 39.161us 1 1 100.00
sram_ctrl_csr_rw 2.000s 47.315us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 15.401us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 40.184us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 1293.434us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 5.000s 969.013us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 280.727us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 5.000s 969.013us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 280.727us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 5.000s 973.430us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 5.000s 973.430us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 47.315us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 13.000s 465.388us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 13.000s 465.388us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 13.000s 465.388us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 7.000s 2627.128us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3601.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 1293.434us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 97.080us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 97.080us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 13.000s 465.388us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 5.000s 969.013us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 7.000s 2627.128us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 5.000s 969.013us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 5.000s 969.013us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 97.080us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 5.000s 969.013us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 33.000s 5506.350us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 55131362082707730140458051527402732732017247902534995599890778486510611001710 None
sram_ctrl_mubi_enc_err 12629037736058083850525804858184943911380402180387117267963852927710698683594 None