Simulation Results: uart

 
08/09/2026 15:31:51 DVSim: v1.52.1 sha: 82334bf json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 93.35 %
  • code
  • 92.53 %
  • assert
  • 96.83 %
  • func
  • 90.69 %
  • block
  • 98.83 %
  • line
  • 99.24 %
  • branch
  • 97.79 %
  • toggle
  • 73.08 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 9.000s 6062.490us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 2.000s 15.735us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 1.000s 21.611us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 3.000s 1749.453us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 1.000s 22.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.000s 25.047us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 1.000s 21.611us 1 1 100.00
uart_csr_aliasing 1.000s 22.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 83.000s 74585.883us 1 1 100.00
parity 2 2 100.00
uart_smoke 9.000s 6062.490us 1 1 100.00
uart_tx_rx 83.000s 74585.883us 1 1 100.00
parity_error 2 2 100.00
uart_intr 39.000s 47850.774us 1 1 100.00
uart_rx_parity_err 117.000s 65756.383us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 83.000s 74585.883us 1 1 100.00
uart_intr 39.000s 47850.774us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 31.000s 15650.992us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 210.000s 114110.546us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 214.000s 57635.679us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 39.000s 47850.774us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 39.000s 47850.774us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 39.000s 47850.774us 1 1 100.00
perf 1 1 100.00
uart_perf 175.000s 25121.908us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 5.000s 2055.323us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 5.000s 2055.323us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 3.000s 2556.230us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 6.000s 1956.269us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 6.000s 1126.743us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 9.000s 5909.647us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 220.000s 130455.998us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 302.000s 188013.054us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 1.000s 39.135us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 1.000s 37.494us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 2.000s 104.239us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 2.000s 104.239us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 2.000s 15.735us 1 1 100.00
uart_csr_rw 1.000s 21.611us 1 1 100.00
uart_csr_aliasing 1.000s 22.000us 1 1 100.00
uart_same_csr_outstanding 1.000s 118.950us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 2.000s 15.735us 1 1 100.00
uart_csr_rw 1.000s 21.611us 1 1 100.00
uart_csr_aliasing 1.000s 22.000us 1 1 100.00
uart_same_csr_outstanding 1.000s 118.950us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 2.000s 72.488us 1 1 100.00
uart_tl_intg_err 2.000s 95.042us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 2.000s 95.042us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 28.000s 3391.895us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:443) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr 1 test run
uart_noise_filter 34021713492867837462049031929205285086014023521231934777863653504881415194237 83
UVM_ERROR @ 298120407 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 298120407 ps: (csr_utils_pkg.sv:463) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 384181530 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
UVM_ERROR @ 426222524 ps: (uart_scoreboard.sv:499) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0, clk_pulses: 0