Simulation Results: ac_range_check

 
09/09/2026 15:31:43 DVSim: v1.52.2 sha: 629146e json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 82.86 %
  • code
  • 93.03 %
  • assert
  • 97.75 %
  • func
  • 57.79 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 80.91 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 40.000s 1356.211us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 72.000s 4071.991us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 8.000s 36.901us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 8.000s 25.807us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 64.000s 6230.716us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 11.000s 359.079us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 8.000s 110.597us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 8.000s 25.807us 1 1 100.00
ac_range_check_csr_aliasing 11.000s 359.079us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 8.000s 63.642us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 42.000s 1541.626us 1 1 100.00
stress_all 1 1 100.00
ac_range_check_stress_all 218.000s 5088.256us 1 1 100.00
alert_test 1 1 100.00
ac_range_check_alert_test 8.000s 15.158us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 8.000s 42.208us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 5.000s 173.821us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 5.000s 173.821us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 8.000s 36.901us 1 1 100.00
ac_range_check_csr_rw 8.000s 25.807us 1 1 100.00
ac_range_check_csr_aliasing 11.000s 359.079us 1 1 100.00
ac_range_check_same_csr_outstanding 7.000s 168.586us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 8.000s 36.901us 1 1 100.00
ac_range_check_csr_rw 8.000s 25.807us 1 1 100.00
ac_range_check_csr_aliasing 11.000s 359.079us 1 1 100.00
ac_range_check_same_csr_outstanding 7.000s 168.586us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 18.000s 3632.280us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 18.000s 3632.280us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 18.000s 3632.280us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 18.000s 3632.280us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 130.000s 4558.431us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 5.000s 32.847us 1 1 100.00
ac_range_check_tl_intg_err 8.000s 260.886us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 385.000s 1845.696us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 33.000s 2504.647us 1 1 100.00