Simulation Results: aes/gcm_unmasked

 
09/09/2026 15:31:43 DVSim: v1.52.2 sha: 629146e json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 83.46 %
  • code
  • 91.18 %
  • assert
  • 97.94 %
  • func
  • 61.27 %
  • block
  • 90.57 %
  • line
  • 92.54 %
  • branch
  • 83.41 %
  • toggle
  • 97.99 %
  • FSM
  • 90.78 %
Validation stages
V1
100.00%
V2
88.24%
V2S
75.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 57.682us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 99.686us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 63.347us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 71.791us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 6.000s 256.013us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 72.116us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 70.371us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 71.791us 1 1 100.00
aes_csr_aliasing 2.000s 72.116us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 99.686us 1 1 100.00
aes_config_error 3.000s 73.074us 1 1 100.00
aes_stress 3.000s 81.532us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 99.686us 1 1 100.00
aes_config_error 3.000s 73.074us 1 1 100.00
aes_stress 3.000s 81.532us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 81.532us 1 1 100.00
aes_b2b 2.000s 82.756us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 81.532us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 2.000s 99.686us 1 1 100.00
aes_config_error 3.000s 73.074us 1 1 100.00
aes_stress 3.000s 81.532us 1 1 100.00
aes_alert_reset 3.000s 208.890us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 2.000s 81.086us 1 1 100.00
aes_config_error 3.000s 73.074us 1 1 100.00
aes_alert_reset 3.000s 208.890us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 4.000s 105.216us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 5.000s 225.231us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 3.000s 208.890us 0 1 0.00
stress 1 1 100.00
aes_stress 3.000s 81.532us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 81.532us 1 1 100.00
aes_sideload 2.000s 74.021us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 4.000s 600.370us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 10801.000s 0.000us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 62.527us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 92.662us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 92.662us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 63.347us 1 1 100.00
aes_csr_rw 2.000s 71.791us 1 1 100.00
aes_csr_aliasing 2.000s 72.116us 1 1 100.00
aes_same_csr_outstanding 2.000s 61.036us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 63.347us 1 1 100.00
aes_csr_rw 2.000s 71.791us 1 1 100.00
aes_csr_aliasing 2.000s 72.116us 1 1 100.00
aes_same_csr_outstanding 2.000s 61.036us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 327.549us 1 1 100.00
fault_inject 1 3 33.33
aes_fi 4.000s 160.541us 0 1 0.00
aes_control_fi 33.000s 10005.869us 0 1 0.00
aes_cipher_fi 2.000s 63.704us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 164.213us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 164.213us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 164.213us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 164.213us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 147.065us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 755.924us 1 1 100.00
aes_tl_intg_err 2.000s 257.486us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 257.486us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 3.000s 208.890us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 164.213us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 164.213us 1 1 100.00
sec_cm_main_config_sparse 2 4 50.00
aes_smoke 2.000s 99.686us 1 1 100.00
aes_stress 3.000s 81.532us 1 1 100.00
aes_alert_reset 3.000s 208.890us 0 1 0.00
aes_core_fi 1407.000s 200000.000us 0 1 0.00
sec_cm_gcm_config_sparse 2 3 66.67
aes_config_error 3.000s 73.074us 1 1 100.00
aes_stress 3.000s 81.532us 1 1 100.00
aes_core_fi 1407.000s 200000.000us 0 1 0.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 164.213us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 56.903us 1 1 100.00
aes_stress 3.000s 81.532us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 81.532us 1 1 100.00
aes_sideload 2.000s 74.021us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 56.903us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 56.903us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 56.903us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 56.903us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 56.903us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 81.532us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 81.532us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 4.000s 160.541us 0 1 0.00
sec_cm_main_fsm_redun 2 4 50.00
aes_fi 4.000s 160.541us 0 1 0.00
aes_control_fi 33.000s 10005.869us 0 1 0.00
aes_cipher_fi 2.000s 63.704us 1 1 100.00
aes_ctr_fi 2.000s 140.102us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 4.000s 160.541us 0 1 0.00
sec_cm_cipher_fsm_redun 1 3 33.33
aes_fi 4.000s 160.541us 0 1 0.00
aes_control_fi 33.000s 10005.869us 0 1 0.00
aes_cipher_fi 2.000s 63.704us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 63.704us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 4.000s 160.541us 0 1 0.00
sec_cm_ctr_fsm_redun 1 3 33.33
aes_fi 4.000s 160.541us 0 1 0.00
aes_control_fi 33.000s 10005.869us 0 1 0.00
aes_ctr_fi 2.000s 140.102us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 4.000s 160.541us 0 1 0.00
sec_cm_ctrl_sparse 2 4 50.00
aes_fi 4.000s 160.541us 0 1 0.00
aes_control_fi 33.000s 10005.869us 0 1 0.00
aes_cipher_fi 2.000s 63.704us 1 1 100.00
aes_ctr_fi 2.000s 140.102us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 3.000s 208.890us 0 1 0.00
sec_cm_main_fsm_local_esc 2 4 50.00
aes_fi 4.000s 160.541us 0 1 0.00
aes_control_fi 33.000s 10005.869us 0 1 0.00
aes_cipher_fi 2.000s 63.704us 1 1 100.00
aes_ctr_fi 2.000s 140.102us 1 1 100.00
sec_cm_cipher_fsm_local_esc 2 4 50.00
aes_fi 4.000s 160.541us 0 1 0.00
aes_control_fi 33.000s 10005.869us 0 1 0.00
aes_cipher_fi 2.000s 63.704us 1 1 100.00
aes_ctr_fi 2.000s 140.102us 1 1 100.00
sec_cm_ctr_fsm_local_esc 1 3 33.33
aes_fi 4.000s 160.541us 0 1 0.00
aes_control_fi 33.000s 10005.869us 0 1 0.00
aes_ctr_fi 2.000s 140.102us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 4.000s 160.541us 0 1 0.00
sec_cm_data_reg_local_esc 1 3 33.33
aes_fi 4.000s 160.541us 0 1 0.00
aes_control_fi 33.000s 10005.869us 0 1 0.00
aes_cipher_fi 2.000s 63.704us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 2.000s 38.540us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error 1 test run
aes_alert_reset 39877937648077867492682562722946046290498025268311410907737693660088841253313 678
UVM_INFO @ 208889678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 1 test run
aes_fi 48439870861566565823405459971258617437952693576045951674786388395959050813961 6763
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 5
----| Seen: 4
----| Expected corrupted: 0
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! 1 test run
aes_control_fi 104367760427416627280179045674961133400081871205327332188828503683501894385357 152
UVM_INFO @ 10005868978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
aes_core_fi 63987440655484587463199716147384890946168968805988091459078172299800915480431 146
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
aes_stress_all 56236354921517828609230540144568595430038551305690946558199767769874125807482 None
UVM_FATAL (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 45836564086057641035027058746757607343427916979476496227395265792371741311130 168
UVM_INFO @ 38540074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---