Simulation Results: aon_timer

 
09/09/2026 15:31:43 DVSim: v1.52.2 sha: 629146e json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 94.49 %
  • code
  • 89.98 %
  • assert
  • 97.62 %
  • func
  • 95.88 %
  • block
  • 99.10 %
  • line
  • 98.91 %
  • branch
  • 98.58 %
  • toggle
  • 72.45 %
Validation stages
V1
100.00%
V2
100.00%
V2S
50.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
aon_timer_smoke 3.000s 506.222us 1 1 100.00
csr_hw_reset 1 1 100.00
aon_timer_csr_hw_reset 2.000s 690.282us 1 1 100.00
csr_rw 1 1 100.00
aon_timer_csr_rw 2.000s 389.734us 1 1 100.00
csr_bit_bash 1 1 100.00
aon_timer_csr_bit_bash 10.000s 7067.818us 1 1 100.00
csr_aliasing 1 1 100.00
aon_timer_csr_aliasing 2.000s 579.006us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aon_timer_csr_mem_rw_with_rand_reset 2.000s 533.574us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aon_timer_csr_rw 2.000s 389.734us 1 1 100.00
aon_timer_csr_aliasing 2.000s 579.006us 1 1 100.00
mem_walk 1 1 100.00
aon_timer_mem_walk 1.000s 417.921us 1 1 100.00
mem_partial_access 1 1 100.00
aon_timer_mem_partial_access 2.000s 484.633us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
prescaler 1 1 100.00
aon_timer_prescaler 7.000s 3705.047us 1 1 100.00
jump 1 1 100.00
aon_timer_jump 1.000s 569.331us 1 1 100.00
stress_all 1 1 100.00
aon_timer_stress_all 11.000s 26384.733us 1 1 100.00
alert_test 1 1 100.00
aon_timer_alert_test 2.000s 320.230us 1 1 100.00
intr_test 1 1 100.00
aon_timer_intr_test 2.000s 314.191us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aon_timer_tl_errors 3.000s 384.409us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aon_timer_tl_errors 3.000s 384.409us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aon_timer_csr_hw_reset 2.000s 690.282us 1 1 100.00
aon_timer_csr_rw 2.000s 389.734us 1 1 100.00
aon_timer_csr_aliasing 2.000s 579.006us 1 1 100.00
aon_timer_same_csr_outstanding 3.000s 2768.982us 1 1 100.00
tl_d_partial_access 4 4 100.00
aon_timer_csr_hw_reset 2.000s 690.282us 1 1 100.00
aon_timer_csr_rw 2.000s 389.734us 1 1 100.00
aon_timer_csr_aliasing 2.000s 579.006us 1 1 100.00
aon_timer_same_csr_outstanding 3.000s 2768.982us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
aon_timer_sec_cm 6.000s 8022.594us 1 1 100.00
aon_timer_tl_intg_err 2.000s 873.890us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
aon_timer_tl_intg_err 2.000s 873.890us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_threshold 1 1 100.00
aon_timer_smoke_max_thold 3.000s 717.605us 1 1 100.00
min_threshold 1 1 100.00
aon_timer_smoke_min_thold 2.000s 672.264us 1 1 100.00
wkup_count_hi_cdc 1 1 100.00
aon_timer_wkup_count_cdc_hi 6.000s 3256.715us 1 1 100.00
custom_intr 1 1 100.00
aon_timer_custom_intr 2.000s 470.182us 1 1 100.00
alternating_on_off 1 1 100.00
aon_timer_alternating_enable_on_off 12.000s 4068.701us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
aon_timer_stress_all_with_rand_reset 16.000s 33465.211us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1059) virtual_sequencer [aon_timer_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
aon_timer_tl_intg_err 78554780767685855586230358257781589842374905457802113621351011732510835813192 98
UVM_INFO @ 873890302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---