Simulation Results: clkmgr

 
09/09/2026 15:31:43 DVSim: v1.52.2 sha: 629146e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 76.33 %
  • code
  • 69.19 %
  • assert
  • 89.88 %
  • func
  • 69.92 %
  • line
  • 82.32 %
  • branch
  • 87.53 %
  • cond
  • 78.76 %
  • toggle
  • 97.36 %
  • FSM
  • 0.00 %
Validation stages
V1
33.33%
V2
53.85%
V2S
37.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.070s 28.365us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 2.230s 141.673us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.960s 4.068us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 2.700s 123.661us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.910s 5.075us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 0.940s 8.565us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 0 2 0.00
clkmgr_csr_rw 0.960s 4.068us 0 1 0.00
clkmgr_csr_aliasing 0.910s 5.075us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 1.050s 12.706us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.210s 25.477us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 1.110s 39.808us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.070s 28.365us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.970s 8.326us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.870s 3.887us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.970s 8.326us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 1.710s 80.968us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 1.170s 26.913us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 3.910s 159.890us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 3.910s 159.890us 1 1 100.00
tl_d_outstanding_access 1 4 25.00
clkmgr_csr_hw_reset 2.230s 141.673us 1 1 100.00
clkmgr_csr_rw 0.960s 4.068us 0 1 0.00
clkmgr_csr_aliasing 0.910s 5.075us 0 1 0.00
clkmgr_same_csr_outstanding 0.990s 6.381us 0 1 0.00
tl_d_partial_access 1 4 25.00
clkmgr_csr_hw_reset 2.230s 141.673us 1 1 100.00
clkmgr_csr_rw 0.960s 4.068us 0 1 0.00
clkmgr_csr_aliasing 0.910s 5.075us 0 1 0.00
clkmgr_same_csr_outstanding 0.990s 6.381us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 4.250s 320.723us 1 1 100.00
clkmgr_tl_intg_err 0.810s 2.441us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 3.600s 208.938us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 3.600s 208.938us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 3.600s 208.938us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 3.600s 208.938us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.930s 11.960us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.810s 2.441us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.970s 8.326us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.870s 3.887us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 3.600s 208.938us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 4.290s 242.628us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.960s 4.068us 0 1 0.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 4.250s 320.723us 1 1 100.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.960s 4.068us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.960s 4.068us 0 1 0.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 4.250s 320.723us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.870s 2.964us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 1.520s 23.263us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 4 test runs
clkmgr_shadow_reg_errors_with_csr_rw 91499347853934116125550002672660794694977797505368694856846952545604200165297 81
UVM_INFO @ 11960430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 86239088519983459034670852357872542357662847454709289686761204001387778791046 81
UVM_INFO @ 2440865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_rw 12520903553570537465402543659164225298996389124016782775193276899611555439136 81
UVM_INFO @ 4067968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_aliasing 71001108423349132833784515773708700349781470944207861099551744943564499613833 83
UVM_INFO @ 5074890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency 28985242053855536643212168589459702830299083675659255261534691423418073229125 82
UVM_INFO @ 8325855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 62711037206964425857363493307104094060248410258917704183562666552387159266016 81
UVM_INFO @ 80967857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency_timeout 47246768817557122804154613586829651231673021193184648386696695066697468977375 84
UVM_INFO @ 3887453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 2487450969885259339309734808591320241274178031608745171306344006672644878258 103
UVM_INFO @ 23263048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:254) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en 1 test run
clkmgr_regwen 42842429384190986776671233341061110834400321645961783208968543731258871268017 80
UVM_INFO @ 2964486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 105988424749408865041935957392349666285535635859794059894409640551525439681300 81
UVM_INFO @ 123661402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 111530274541014546292323511670262465856889969450783891285731089688595815954748 81
UVM_INFO @ 6381122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 1 test run
clkmgr_csr_mem_rw_with_rand_reset 39851377021573727894002960239960439252006916854183183733987716342208119262162 82
UVM_INFO @ 8564728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---