Simulation Results: csrng

 
09/09/2026 15:31:43 DVSim: v1.52.2 sha: 629146e json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 90.29 %
  • code
  • 92.36 %
  • assert
  • 94.54 %
  • func
  • 83.96 %
  • block
  • 97.03 %
  • line
  • 97.84 %
  • branch
  • 92.64 %
  • toggle
  • 93.24 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 3.000s 30.690us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 12.808us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 3.000s 70.880us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 47.000s 2563.241us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 2.000s 20.595us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 3.000s 82.570us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 3.000s 70.880us 1 1 100.00
csrng_csr_aliasing 2.000s 20.595us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 7.000s 208.960us 1 1 100.00
alerts 1 1 100.00
csrng_alert 5.000s 107.084us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 44.217us 1 1 100.00
cmds 1 1 100.00
csrng_cmds 21.000s 529.510us 1 1 100.00
life cycle 1 1 100.00
csrng_cmds 21.000s 529.510us 1 1 100.00
stress_all 1 1 100.00
csrng_stress_all 306.000s 15225.795us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 26.162us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 23.135us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 4.000s 162.630us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 4.000s 162.630us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 12.808us 1 1 100.00
csrng_csr_rw 3.000s 70.880us 1 1 100.00
csrng_csr_aliasing 2.000s 20.595us 1 1 100.00
csrng_same_csr_outstanding 4.000s 126.066us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 12.808us 1 1 100.00
csrng_csr_rw 3.000s 70.880us 1 1 100.00
csrng_csr_aliasing 2.000s 20.595us 1 1 100.00
csrng_same_csr_outstanding 4.000s 126.066us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 5.000s 89.559us 1 1 100.00
csrng_tl_intg_err 5.000s 276.755us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 2.000s 22.630us 1 1 100.00
csrng_csr_rw 3.000s 70.880us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 5.000s 107.084us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 306.000s 15225.795us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 7.000s 208.960us 1 1 100.00
csrng_err 2.000s 44.217us 1 1 100.00
csrng_sec_cm 5.000s 89.559us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 7.000s 208.960us 1 1 100.00
csrng_err 2.000s 44.217us 1 1 100.00
csrng_sec_cm 5.000s 89.559us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 7.000s 208.960us 1 1 100.00
csrng_err 2.000s 44.217us 1 1 100.00
csrng_sec_cm 5.000s 89.559us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 7.000s 208.960us 1 1 100.00
csrng_err 2.000s 44.217us 1 1 100.00
csrng_sec_cm 5.000s 89.559us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 7.000s 208.960us 1 1 100.00
csrng_err 2.000s 44.217us 1 1 100.00
csrng_sec_cm 5.000s 89.559us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 5.000s 107.084us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 7.000s 208.960us 1 1 100.00
csrng_err 2.000s 44.217us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 306.000s 15225.795us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 5.000s 107.084us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 5.000s 276.755us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 7.000s 208.960us 1 1 100.00
csrng_err 2.000s 44.217us 1 1 100.00
csrng_sec_cm 5.000s 89.559us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 7.000s 208.960us 1 1 100.00
csrng_err 2.000s 44.217us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 7.000s 208.960us 1 1 100.00
csrng_err 2.000s 44.217us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 7.000s 208.960us 1 1 100.00
csrng_err 2.000s 44.217us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 7.000s 208.960us 1 1 100.00
csrng_err 2.000s 44.217us 1 1 100.00
csrng_sec_cm 5.000s 89.559us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 7.000s 208.960us 1 1 100.00
csrng_err 2.000s 44.217us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 2.000s 10.428us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:1230) [csrng_common_vseq] Check failed (vseq_done) 1 test run
csrng_stress_all_with_rand_reset 79009674872211766696398258851645351985589417454314875311025198713134415877021 107
UVM_INFO @ 10428485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---