Simulation Results: dma

 
09/09/2026 15:31:43 DVSim: v1.52.2 sha: 629146e json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 82.21 %
  • code
  • 90.41 %
  • assert
  • 96.50 %
  • func
  • 59.71 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 77.37 %
  • FSM
  • 91.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 5.000s 780.829us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 7.000s 650.014us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 7.000s 317.642us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 72.297us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 2.000s 51.420us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 9.000s 805.045us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 2.000s 262.870us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 27.631us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 2.000s 51.420us 1 1 100.00
dma_csr_aliasing 2.000s 262.870us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 43.000s 2584.738us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 799.000s 274947.654us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 203.000s 51132.475us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 203.000s 51132.475us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 799.000s 274947.654us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 211.000s 29044.522us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 203.000s 51132.475us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 5.000s 2649.459us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 142.000s 9308.909us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 2.000s 20.572us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 2.000s 17.423us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 3.000s 133.188us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 3.000s 133.188us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 72.297us 1 1 100.00
dma_csr_rw 2.000s 51.420us 1 1 100.00
dma_csr_aliasing 2.000s 262.870us 1 1 100.00
dma_same_csr_outstanding 3.000s 43.639us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 72.297us 1 1 100.00
dma_csr_rw 2.000s 51.420us 1 1 100.00
dma_csr_aliasing 2.000s 262.870us 1 1 100.00
dma_same_csr_outstanding 3.000s 43.639us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 26.000s 350.318us 1 1 100.00
dma_generic_stress 211.000s 29044.522us 1 1 100.00
dma_handshake_stress 203.000s 51132.475us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 12.000s 1242.821us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 4.000s 729.448us 1 1 100.00
dma_sec_cm 1.000s 13.388us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 165.000s 14949.752us 1 1 100.00
dma_longer_transfer 5.000s 730.261us 1 1 100.00
dma_stress_all_with_rand_reset 6.000s 218.669us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1297) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 16698514176303196463742953616815498811556242503810340241143391453891028247294 95
UVM_INFO @ 218669088ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---