Simulation Results: edn/edn0

 
09/09/2026 15:31:43 DVSim: v1.52.2 sha: 629146e json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 75.38 %
  • code
  • 82.13 %
  • assert
  • 95.35 %
  • func
  • 48.67 %
  • block
  • 93.90 %
  • line
  • 96.68 %
  • branch
  • 86.85 %
  • toggle
  • 67.49 %
  • FSM
  • 77.52 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 2.000s 63.498us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 2.000s 43.363us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 2.000s 12.014us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.000s 437.874us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.000s 32.222us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 3.000s 53.139us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 2.000s 12.014us 1 1 100.00
edn_csr_aliasing 1.000s 32.222us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.000s 33.320us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.000s 33.320us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.000s 33.320us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.000s 27.892us 1 1 100.00
alerts 1 1 100.00
edn_alert 2.000s 26.144us 1 1 100.00
errs 1 1 100.00
edn_err 2.000s 38.721us 1 1 100.00
disable 2 2 100.00
edn_disable 2.000s 14.462us 1 1 100.00
edn_disable_auto_req_mode 2.000s 59.147us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 9.000s 500.855us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.000s 16.473us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.000s 55.487us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 4.000s 101.246us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 4.000s 101.246us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 2.000s 43.363us 1 1 100.00
edn_csr_rw 2.000s 12.014us 1 1 100.00
edn_csr_aliasing 1.000s 32.222us 1 1 100.00
edn_same_csr_outstanding 3.000s 144.593us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 2.000s 43.363us 1 1 100.00
edn_csr_rw 2.000s 12.014us 1 1 100.00
edn_csr_aliasing 1.000s 32.222us 1 1 100.00
edn_same_csr_outstanding 3.000s 144.593us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 10.000s 1468.173us 1 1 100.00
edn_tl_intg_err 3.000s 200.286us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 2.000s 21.009us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 2.000s 26.144us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 10.000s 1468.173us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 10.000s 1468.173us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 10.000s 1468.173us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 10.000s 1468.173us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 2.000s 26.144us 1 1 100.00
edn_sec_cm 10.000s 1468.173us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 2.000s 26.144us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 3.000s 200.286us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 73.000s 4132.300us 1 1 100.00