Simulation Results: edn/edn1

 
09/09/2026 15:31:43 DVSim: v1.52.2 sha: 629146e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.64 %
  • code
  • 81.65 %
  • assert
  • 98.44 %
  • func
  • 79.83 %
  • line
  • 97.72 %
  • branch
  • 92.21 %
  • cond
  • 88.85 %
  • toggle
  • 87.42 %
  • FSM
  • 42.05 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.250s 17.667us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.060s 148.839us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.950s 30.330us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.880s 161.551us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.120s 41.907us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 2.140s 44.834us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.950s 30.330us 1 1 100.00
edn_csr_aliasing 1.120s 41.907us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.520s 46.729us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.520s 46.729us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.520s 46.729us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.090s 23.633us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.400s 95.750us 1 1 100.00
errs 1 1 100.00
edn_err 1.030s 35.101us 1 1 100.00
disable 2 2 100.00
edn_disable 1.010s 25.264us 1 1 100.00
edn_disable_auto_req_mode 1.480s 37.169us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.650s 63.835us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.170s 47.590us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.170s 15.502us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.810s 43.453us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.810s 43.453us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.060s 148.839us 1 1 100.00
edn_csr_rw 0.950s 30.330us 1 1 100.00
edn_csr_aliasing 1.120s 41.907us 1 1 100.00
edn_same_csr_outstanding 1.480s 39.711us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.060s 148.839us 1 1 100.00
edn_csr_rw 0.950s 30.330us 1 1 100.00
edn_csr_aliasing 1.120s 41.907us 1 1 100.00
edn_same_csr_outstanding 1.480s 39.711us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.440s 226.166us 1 1 100.00
edn_tl_intg_err 1.690s 211.912us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.220s 41.502us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.400s 95.750us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.440s 226.166us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.440s 226.166us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.440s 226.166us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.440s 226.166us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.400s 95.750us 1 1 100.00
edn_sec_cm 3.440s 226.166us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.400s 95.750us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.690s 211.912us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 40.590s 1873.628us 1 1 100.00