Simulation Results: entropy_src/rng_16bits

 
09/09/2026 15:31:43 DVSim: v1.52.2 sha: 629146e json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 68.92 %
  • code
  • 83.11 %
  • assert
  • 73.92 %
  • func
  • 49.74 %
  • block
  • 94.18 %
  • line
  • 97.84 %
  • branch
  • 86.25 %
  • toggle
  • 52.51 %
  • FSM
  • 95.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 3.000s 20.009us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 2.000s 24.418us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 2.000s 51.721us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 21.000s 1654.768us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 2.000s 135.479us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
entropy_src_csr_mem_rw_with_rand_reset 2.000s 30.614us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 2.000s 51.721us 1 1 100.00
entropy_src_csr_aliasing 2.000s 135.479us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 3.000s 20.009us 1 1 100.00
entropy_src_rng 103.000s 13050.551us 1 1 100.00
entropy_src_fw_ov 117.000s 13231.523us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 117.000s 13231.523us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 103.000s 13050.551us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 711.000s 13041.687us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 103.000s 13050.551us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 103.000s 13050.551us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 103.000s 13050.551us 1 1 100.00
entropy_src_intr 30.000s 3073.704us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 103.000s 13050.551us 1 1 100.00
entropy_src_functional_alerts 7.000s 204.828us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 259.000s 14302.907us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 3.000s 101.430us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 4.000s 83.950us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 2.000s 43.590us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 40.292us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 5.000s 60.951us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 5.000s 60.951us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 24.418us 1 1 100.00
entropy_src_csr_rw 2.000s 51.721us 1 1 100.00
entropy_src_csr_aliasing 2.000s 135.479us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 55.684us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 24.418us 1 1 100.00
entropy_src_csr_rw 2.000s 51.721us 1 1 100.00
entropy_src_csr_aliasing 2.000s 135.479us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 55.684us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 3.000s 57.738us 1 1 100.00
entropy_src_tl_intg_err 4.000s 164.073us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 103.000s 13050.551us 1 1 100.00
entropy_src_cfg_regwen 2.000s 29.971us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 103.000s 13050.551us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 103.000s 13050.551us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 103.000s 13050.551us 1 1 100.00
entropy_src_fw_ov 117.000s 13231.523us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 3.000s 101.430us 1 1 100.00
entropy_src_sec_cm 3.000s 57.738us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 3.000s 101.430us 1 1 100.00
entropy_src_sec_cm 3.000s 57.738us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 103.000s 13050.551us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 3.000s 101.430us 1 1 100.00
entropy_src_sec_cm 3.000s 57.738us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 3.000s 101.430us 1 1 100.00
entropy_src_sec_cm 3.000s 57.738us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 3.000s 101.430us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 7.000s 204.828us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 4.000s 164.073us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 264.000s 13200.821us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 22.000s 1808.648us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1661) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.alert_test 1 test run
entropy_src_stress_all_with_rand_reset 94716429686475900893991042972416598445303449272430846576688620761456074052811 129
UVM_INFO @ 1808648100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---