Simulation Results: hmac

 
09/09/2026 15:31:43 DVSim: v1.52.2 sha: 629146e json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 69.66 %
  • code
  • 83.32 %
  • assert
  • 96.96 %
  • func
  • 28.70 %
  • block
  • 97.65 %
  • line
  • 98.44 %
  • branch
  • 94.11 %
  • toggle
  • 45.89 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 8.000s 7547.454us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 2.000s 164.337us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 1.000s 20.519us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 22.000s 8122.822us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 3.000s 353.804us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 581.000s 215697.552us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 1.000s 20.519us 1 1 100.00
hmac_csr_aliasing 3.000s 353.804us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 51.000s 2107.404us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 35.000s 2471.594us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 338.000s 18445.236us 1 1 100.00
hmac_test_sha384_vectors 37.000s 768.452us 1 1 100.00
hmac_test_sha512_vectors 518.000s 16305.658us 1 1 100.00
hmac_test_hmac256_vectors 13.000s 1011.881us 1 1 100.00
hmac_test_hmac384_vectors 16.000s 1505.254us 1 1 100.00
hmac_test_hmac512_vectors 19.000s 1306.665us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 34.000s 1467.634us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 332.000s 14383.764us 1 1 100.00
error 1 1 100.00
hmac_error 134.000s 9332.784us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 12.000s 840.580us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 8.000s 7547.454us 1 1 100.00
hmac_long_msg 51.000s 2107.404us 1 1 100.00
hmac_back_pressure 35.000s 2471.594us 1 1 100.00
hmac_datapath_stress 332.000s 14383.764us 1 1 100.00
hmac_burst_wr 34.000s 1467.634us 1 1 100.00
hmac_stress_all 196.000s 4773.923us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 8.000s 7547.454us 1 1 100.00
hmac_long_msg 51.000s 2107.404us 1 1 100.00
hmac_back_pressure 35.000s 2471.594us 1 1 100.00
hmac_datapath_stress 332.000s 14383.764us 1 1 100.00
hmac_wipe_secret 12.000s 840.580us 1 1 100.00
hmac_test_sha256_vectors 338.000s 18445.236us 1 1 100.00
hmac_test_sha384_vectors 37.000s 768.452us 1 1 100.00
hmac_test_sha512_vectors 518.000s 16305.658us 1 1 100.00
hmac_test_hmac256_vectors 13.000s 1011.881us 1 1 100.00
hmac_test_hmac384_vectors 16.000s 1505.254us 1 1 100.00
hmac_test_hmac512_vectors 19.000s 1306.665us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 8.000s 7547.454us 1 1 100.00
hmac_long_msg 51.000s 2107.404us 1 1 100.00
hmac_back_pressure 35.000s 2471.594us 1 1 100.00
hmac_datapath_stress 332.000s 14383.764us 1 1 100.00
hmac_burst_wr 34.000s 1467.634us 1 1 100.00
hmac_error 134.000s 9332.784us 1 1 100.00
hmac_wipe_secret 12.000s 840.580us 1 1 100.00
hmac_test_sha256_vectors 338.000s 18445.236us 1 1 100.00
hmac_test_sha384_vectors 37.000s 768.452us 1 1 100.00
hmac_test_sha512_vectors 518.000s 16305.658us 1 1 100.00
hmac_test_hmac256_vectors 13.000s 1011.881us 1 1 100.00
hmac_test_hmac384_vectors 16.000s 1505.254us 1 1 100.00
hmac_test_hmac512_vectors 19.000s 1306.665us 1 1 100.00
hmac_stress_all 196.000s 4773.923us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 196.000s 4773.923us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 1.000s 41.650us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 2.000s 12.751us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 4.000s 542.450us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 4.000s 542.450us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 2.000s 164.337us 1 1 100.00
hmac_csr_rw 1.000s 20.519us 1 1 100.00
hmac_csr_aliasing 3.000s 353.804us 1 1 100.00
hmac_same_csr_outstanding 2.000s 47.850us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 2.000s 164.337us 1 1 100.00
hmac_csr_rw 1.000s 20.519us 1 1 100.00
hmac_csr_aliasing 3.000s 353.804us 1 1 100.00
hmac_same_csr_outstanding 2.000s 47.850us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 2.000s 143.453us 1 1 100.00
hmac_tl_intg_err 2.000s 559.356us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.000s 559.356us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 8.000s 7547.454us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 5.000s 404.560us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 57.000s 2605.307us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 4.000s 364.952us 1 1 100.00