Simulation Results

Simulation Results: i2c

09/09/2026 15:31:43 DVSim: v1.52.2 sha: 629146e json Branch: master Tool: xcelium [24.03-s007]

Coverage statistics

Total
87.90 %

code
85.93 %

assert
97.04 %

func
80.72 %

block
96.03 %

line
95.43 %

branch
92.88 %

toggle
72.68 %

FSM
82.73 %

Validation stages

V1		100.00%
V2		80.49%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	63.000s	2065.718us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	22.000s	3476.244us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	1.000s	87.911us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	2.000s	43.375us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	6.000s	173.575us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.000s	200.625us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	2.000s	66.102us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	2.000s	43.375us	1	1	100.00
	i2c_csr_aliasing	1.000s	200.625us	1	1	100.00

33/41 passed

80.49 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				1	1	100.00
	i2c_host_error_intr	3.000s	61.517us	1	1	100.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	3600.000s	0.000us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	342.000s	2986.691us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	2.000s	17.185us	1	1	100.00
host_fifo_watermark				0	1	0.00
	i2c_host_fifo_watermark	3600.000s	0.000us	0	1	0.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	1556.000s	8406.218us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	2.000s	1584.503us	1	1	100.00
	i2c_host_fifo_fmt_empty	7.000s	223.393us	1	1	100.00
	i2c_host_fifo_reset_rx	4.000s	160.896us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	541.000s	1888.307us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	16.000s	6257.970us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	2.000s	190.078us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	4.000s	503.944us	0	1	0.00
target_stress_all				0	1	0.00
	i2c_target_stress_all	3600.000s	0.000us	0	1	0.00
target_maxperf				1	1	100.00
	i2c_target_perf	8.000s	786.614us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	12.000s	613.065us	1	1	100.00
	i2c_target_intr_smoke	7.000s	5721.533us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	2.000s	636.256us	1	1	100.00
	i2c_target_fifo_reset_tx	2.000s	224.390us	1	1	100.00
target_fifo_full				1	3	33.33
	i2c_target_stress_wr	3600.000s	0.000us	0	1	0.00
	i2c_target_stress_rd	12.000s	613.065us	1	1	100.00
	i2c_target_intr_stress_wr	3601.000s	0.000us	0	1	0.00
target_timeout				1	1	100.00
	i2c_target_timeout	8.000s	1262.589us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	2590.000s	2807.576us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	8.000s	3328.741us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	32.000s	10439.877us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	3.000s	748.672us	1	1	100.00
	i2c_target_fifo_watermarks_tx	2.000s	191.086us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	342.000s	2986.691us	1	1	100.00
	i2c_host_perf_precise	29.000s	2338.736us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	16.000s	6257.970us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	2.000s	53.726us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	5.000s	1196.992us	1	1	100.00
	i2c_target_nack_acqfull_addr	4.000s	544.762us	1	1	100.00
	i2c_target_nack_txstretch	3.000s	282.351us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	21.000s	541.493us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	4.000s	464.730us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	2.000s	69.520us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	1.000s	41.456us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	3.000s	81.174us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	3.000s	81.174us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	1.000s	87.911us	1	1	100.00
	i2c_csr_rw	2.000s	43.375us	1	1	100.00
	i2c_csr_aliasing	1.000s	200.625us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	36.765us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	1.000s	87.911us	1	1	100.00
	i2c_csr_rw	2.000s	43.375us	1	1	100.00
	i2c_csr_aliasing	1.000s	200.625us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	36.765us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	2.000s	242.222us	1	1	100.00
	i2c_sec_cm	2.000s	133.886us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	2.000s	242.222us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	33.000s	8079.286us	1
target_error_intr				1
	i2c_target_unexp_stop	3.000s	843.964us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	2.000s	21.687us	1

Error Messages

	Test	seed	line	log context
Job timed out after * minutes				5 test runs
	i2c_host_fifo_watermark	32981733523382437576834528780718826822380964205824568952504384552151495763299	None
	i2c_host_stress_all	53060193316997376465012677558463395775614923853305764914378296704656551879279	None
	i2c_target_stress_wr	74449216177178784192104282272583473618654348520467657025181894067382577338116	None
	i2c_target_intr_stress_wr	74279948812152599247263699990274953594351918545114347225990222580226791696960	None
	i2c_target_stress_all	65104858857432012935001688038049419854638848011944041650214455369163005079691	None
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	68500569542069964193796697781193346575982605266487264211189763493909525951944	93	UVM_INFO @ 503943698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:680) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	35548925735628634487154679543120827625605477031414333595300519175661091504530	87	UVM_INFO @ 843963659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	30128945714800341990498132353363799039405772631701944682916902389942974966153	88	UVM_INFO @ 10439876509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1297) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	92221679225832666309321510239075753553184419246613973030908496815624897711330	103	UVM_INFO @ 8079286154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				1 test run
	i2c_target_stress_all_with_rand_reset	7562209467973003731994384548813165298457639496241498866135418144960574157835	94	UVM_INFO @ 21687354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead				1 test run
	i2c_host_mode_toggle	107688163395521363106711716987328470103843163777781565933657196732054183877827	96	--> EXP: --------------------------------------------------- Name Type Size Value ---------------------------------------------------