Simulation Results: keymgr_dpe/darjeeling

 
09/09/2026 15:31:43 DVSim: v1.52.2 sha: 629146e json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 54.85 %
  • code
  • 58.49 %
  • assert
  • 94.86 %
  • func
  • 11.19 %
  • block
  • 94.44 %
  • line
  • 94.95 %
  • branch
  • 82.63 %
  • toggle
  • 40.99 %
  • FSM
  • 15.38 %
Validation stages
V1
83.33%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 0 1 0.00
keymgr_dpe_smoke 4.000s 208.060us 0 1 0.00
csr_hw_reset 1 1 100.00
keymgr_dpe_csr_hw_reset 1.000s 13.687us 1 1 100.00
csr_rw 1 1 100.00
keymgr_dpe_csr_rw 1.000s 42.823us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_dpe_csr_bit_bash 8.000s 765.044us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_dpe_csr_aliasing 3.000s 41.712us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_dpe_csr_mem_rw_with_rand_reset 2.000s 44.267us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_dpe_csr_rw 1.000s 42.823us 1 1 100.00
keymgr_dpe_csr_aliasing 3.000s 41.712us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
intr_test 1 1 100.00
keymgr_dpe_intr_test 2.000s 55.811us 1 1 100.00
alert_test 1 1 100.00
keymgr_dpe_alert_test 2.000s 52.202us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_dpe_tl_errors 2.000s 205.134us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_dpe_tl_errors 2.000s 205.134us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_dpe_csr_hw_reset 1.000s 13.687us 1 1 100.00
keymgr_dpe_csr_rw 1.000s 42.823us 1 1 100.00
keymgr_dpe_csr_aliasing 3.000s 41.712us 1 1 100.00
keymgr_dpe_same_csr_outstanding 2.000s 44.447us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_dpe_csr_hw_reset 1.000s 13.687us 1 1 100.00
keymgr_dpe_csr_rw 1.000s 42.823us 1 1 100.00
keymgr_dpe_csr_aliasing 3.000s 41.712us 1 1 100.00
keymgr_dpe_same_csr_outstanding 2.000s 44.447us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
keymgr_dpe_sec_cm 8.000s 1392.746us 1 1 100.00
keymgr_dpe_tl_intg_err 4.000s 442.486us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_dpe_shadow_reg_errors 3.000s 174.799us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_dpe_shadow_reg_errors 3.000s 174.799us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_dpe_shadow_reg_errors 3.000s 174.799us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_dpe_shadow_reg_errors 3.000s 174.799us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_dpe_shadow_reg_errors_with_csr_rw 5.000s 123.845us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_dpe_sec_cm 8.000s 1392.746us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_dpe_sec_cm 8.000s 1392.746us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert recov_operation_err has unexpected timeout error 1 test run
keymgr_dpe_smoke 9659729527412808243115329204917920431895292641642663375485642746318116489220 591
UVM_INFO @ 208059998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---