Simulation Results: lc_ctrl/volatile_unlock_disabled

 
09/09/2026 15:31:43 DVSim: v1.52.2 sha: 629146e json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 88.32 %
  • code
  • 90.06 %
  • assert
  • 96.83 %
  • func
  • 78.06 %
  • block
  • 95.94 %
  • line
  • 96.87 %
  • branch
  • 89.66 %
  • toggle
  • 83.25 %
  • FSM
  • 90.48 %
Validation stages
V1
100.00%
V2
70.00%
V2S
60.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 28.963us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 54.653us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 15.435us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 3.000s 111.637us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 30.772us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 26.884us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 15.435us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 30.772us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 7.000s 1477.503us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 22.726us 1 1 100.00
lc_prog_failure 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_errors 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
security_escalation 1 7 14.29
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_security_escalation 6.000s 663.706us 1 1 100.00
lc_ctrl_jtag_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3.000s 242.705us 0 1 0.00
lc_ctrl_jtag_errors 3600.000s 0.000us 0 1 0.00
jtag_access 10 13 76.92
lc_ctrl_jtag_smoke 5.000s 771.855us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3.000s 242.705us 0 1 0.00
lc_ctrl_jtag_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_access 9.000s 1504.501us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 7.000s 563.684us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 423.068us 1 1 100.00
lc_ctrl_jtag_csr_rw 3.000s 294.680us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.000s 1373.296us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.000s 275.972us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 31.299us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.000s 411.863us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 140.212us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 5.000s 2271.800us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 44.244us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 10802.213s 0.000us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 23.333us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 91.752us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 91.752us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 54.653us 1 1 100.00
lc_ctrl_csr_rw 2.000s 15.435us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 30.772us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 20.517us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 54.653us 1 1 100.00
lc_ctrl_csr_rw 2.000s 15.435us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 30.772us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 20.517us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 4.000s 1481.878us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 190.895us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 190.895us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 7.000s 1477.503us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 1481.878us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 1481.878us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 1481.878us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 1481.878us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 1481.878us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 1481.878us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 1481.878us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 1481.878us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.000s 663.706us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
sec_cm_intersig_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 8.000s 741.826us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 598.283us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 598.283us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3600.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 10 test runs
lc_ctrl_state_failure 85484055512684215527616025706417471480943429070216143383428418628820974559685 None
lc_ctrl_state_post_trans 103134821528518034508727834108156773402460783311702320465748351383323961994925 None
lc_ctrl_prog_failure 49702836992002097030011832941167735202344577639748042865463991801391920775828 None
lc_ctrl_errors 38796118618527078488472843252905985227486244236933050526932344596965689030547 None
lc_ctrl_jtag_state_failure 9766317185846055052327714701115703355636886833260287189928251510306275048969 None
lc_ctrl_jtag_state_post_trans 115657073700493859090024267681801904018229396050382050632678143715895844427300 None
lc_ctrl_jtag_errors 54710032483551170608954838842128061109904896073390819275493110240788661280154 None
lc_ctrl_sec_mubi 85593870709642683861101413189074549715905782073272425892327939354573806870792 None
lc_ctrl_stress_all 96926806746892982741268762622318179288132376951179918290935642816332781443526 None
lc_ctrl_stress_all_with_rand_reset 81089152968666271176537399431743349905868745776010156731218678286614211732616 None
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_prog_error has unexpected timeout error 1 test run
lc_ctrl_jtag_prog_failure 60658516183068622415610340711465764713182707570857783363491565475512626157720 176
UVM_INFO @ 242704759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---