Simulation Results: lc_ctrl/volatile_unlock_enabled

 
09/09/2026 15:31:43 DVSim: v1.52.2 sha: 629146e json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 88.72 %
  • code
  • 90.62 %
  • assert
  • 96.83 %
  • func
  • 78.71 %
  • block
  • 96.34 %
  • line
  • 97.21 %
  • branch
  • 90.73 %
  • toggle
  • 79.31 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
73.33%
V2S
60.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 3.000s 140.963us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 36.620us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 52.735us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 3.000s 1390.808us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 46.220us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.000s 19.886us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 52.735us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 46.220us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 7.000s 2768.957us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 14.247us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 3.000s 42.913us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_errors 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
security_escalation 2 7 28.57
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_prog_failure 3.000s 42.913us 1 1 100.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_security_escalation 7.000s 339.610us 1 1 100.00
lc_ctrl_jtag_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 14.000s 5076.984us 0 1 0.00
jtag_access 10 13 76.92
lc_ctrl_jtag_smoke 3.000s 175.115us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 14.000s 5076.984us 0 1 0.00
lc_ctrl_jtag_access 10.000s 1040.158us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 11.000s 1102.432us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.000s 531.893us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 147.108us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 9.000s 1524.833us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.000s 218.325us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 19.390us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 213.902us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 128.103us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 5.000s 667.902us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 59.430us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 10802.209s 0.000us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 107.462us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 531.186us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 531.186us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 36.620us 1 1 100.00
lc_ctrl_csr_rw 2.000s 52.735us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 46.220us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 26.792us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 36.620us 1 1 100.00
lc_ctrl_csr_rw 2.000s 52.735us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 46.220us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 26.792us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 4.000s 767.938us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 73.974us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 73.974us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 7.000s 2768.957us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 767.938us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 767.938us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 767.938us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 767.938us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 767.938us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 767.938us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 767.938us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 767.938us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 7.000s 339.610us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
sec_cm_intersig_mubi 0 1 0.00
lc_ctrl_sec_mubi 3601.000s 0.000us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
lc_ctrl_sec_mubi 3601.000s 0.000us 0 1 0.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.000s 517.463us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.000s 372.753us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.000s 372.753us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3600.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 9 test runs
lc_ctrl_state_failure 90603183339680215235823920871121990150621280621723004591252685219256571331247 None
lc_ctrl_state_post_trans 49720222045160065570365497856610576971592472603085541211088397779878566905884 None
lc_ctrl_errors 49687364764545388907290340903295128438252935199703879060063909110887853290407 None
lc_ctrl_jtag_state_failure 3729129359260250611101371972817553256577942915660457885063365969122972794525 None
lc_ctrl_jtag_state_post_trans 11531344288256091299044173305968397114198841387829919942883899914538843849378 None
lc_ctrl_jtag_prog_failure 73887877475302746404348058442501802091197788565913565692597852095468823917896 None
lc_ctrl_sec_mubi 103258653562681579607843334545735847231517216690990041862615214938041465191997 None
lc_ctrl_stress_all 44956662415106684494580721258223220268344312516457068299798945557798368468853 None
lc_ctrl_stress_all_with_rand_reset 107959273814056185250842932674419572479568096423871353951432825072742262991954 None
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_prog_error has unexpected timeout error 1 test run
lc_ctrl_jtag_errors 2060083699648540079908152944439305194000957689102300440536384986992461694074 993
UVM_INFO @ 5076983609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---