Simulation Results: mbx

 
09/09/2026 15:31:43 DVSim: v1.52.2 sha: 629146e json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 90.44 %
  • code
  • 89.16 %
  • assert
  • 96.96 %
  • func
  • 85.21 %
  • block
  • 96.63 %
  • line
  • 96.64 %
  • branch
  • 91.17 %
  • toggle
  • 79.67 %
Validation stages
V1
100.00%
V2
72.73%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 70.000s 16404.185us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 1.000s 14.101us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 1.000s 22.124us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 3.000s 102.700us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 1.000s 13.156us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
mbx_csr_mem_rw_with_rand_reset 2.000s 46.402us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 1.000s 22.124us 1 1 100.00
mbx_csr_aliasing 1.000s 13.156us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 0 1 0.00
mbx_stress 2.000s 43.044us 0 1 0.00
mbx_max_activity 0 1 0.00
mbx_stress_zero_delays 4.000s 81.371us 0 1 0.00
mbx_imbx_oob 1 1 100.00
mbx_imbx_oob 16.000s 1957.825us 1 1 100.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 9.000s 1490.512us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 2.000s 13.618us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 2.000s 79.724us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 1.000s 16.860us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 1.000s 16.860us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 1.000s 14.101us 1 1 100.00
mbx_csr_rw 1.000s 22.124us 1 1 100.00
mbx_csr_aliasing 1.000s 13.156us 1 1 100.00
mbx_same_csr_outstanding 2.000s 24.825us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 1.000s 14.101us 1 1 100.00
mbx_csr_rw 1.000s 22.124us 1 1 100.00
mbx_csr_aliasing 1.000s 13.156us 1 1 100.00
mbx_same_csr_outstanding 2.000s 24.825us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_tl_intg_err 1.000s 166.327us 1 1 100.00
mbx_sec_cm 1.000s 18.133us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register 1 test run
mbx_stress 64069327949959615962758481954402375893549085772548358496842037134556085179430 89
UVM_INFO @ 43044196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/mbx-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_mbx_*/rtl/mbx_ombx.sv,287): Assertion ReadyAssertedWhenRead_A has failed 1 test run
mbx_stress_zero_delays 36687767824416042924306515274833902013483419547429336371141515687604534405031 246
UVM_ERROR @ 81371322 ps: (mbx_ombx.sv:287) [ASSERT FAILED] ReadyAssertedWhenRead_A
UVM_INFO @ 81371322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:718) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *). 1 test run
mbx_tl_errors 58383043252836713028540639665739816334945767339951493930262021020226487654937 85
TL item was: req: (cip_tl_seq_item@18085) { a_addr: 'ha4ccb710 a_data: 'hdb10e03f a_mask: 'h2 a_size: 'h2 a_param: 'h0 a_source: 'h1c a_opcode: 'h1 a_user: 'h275f6 d_param: 'h0 d_source: 'h1c d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 16860212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---