Simulation Results: otbn

 
09/09/2026 15:31:43 DVSim: v1.52.2 sha: 629146e json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 89.70 %
  • code
  • 81.88 %
  • assert
  • 89.76 %
  • func
  • 97.46 %
  • block
  • 97.70 %
  • line
  • 97.93 %
  • branch
  • 81.62 %
  • toggle
  • 81.77 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
88.24%
V2S
88.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
otbn_smoke 15.000s 48.254us 1 1 100.00
otbn_smoke_vectorized 11.000s 53.452us 1 1 100.00
single_binary 1 1 100.00
otbn_single 8.000s 12.509us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 5.000s 49.400us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 5.000s 45.188us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 8.000s 181.793us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 6.000s 15.908us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 10.000s 1336.239us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 5.000s 45.188us 1 1 100.00
otbn_csr_aliasing 6.000s 15.908us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 143.000s 6186.172us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 34.000s 326.949us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 46.000s 290.810us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 77.000s 187.632us 1 1 100.00
wfi 1 3 33.33
otbn_wfi_smoke 7.000s 15.607us 0 1 0.00
otbn_wfi_sec_wipe 9.000s 38.675us 1 1 100.00
otbn_wfi_back_to_back 6.000s 17.776us 0 1 0.00
back_to_back 1 1 100.00
otbn_multi 70.000s 1416.846us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 112.000s 265.220us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 11.000s 23.618us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 6.000s 10.407us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 12.000s 80.165us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 7.000s 17.548us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 4.000s 14.521us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 7.000s 177.616us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 7.000s 177.616us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 5.000s 49.400us 1 1 100.00
otbn_csr_rw 5.000s 45.188us 1 1 100.00
otbn_csr_aliasing 6.000s 15.908us 1 1 100.00
otbn_same_csr_outstanding 5.000s 78.770us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 5.000s 49.400us 1 1 100.00
otbn_csr_rw 5.000s 45.188us 1 1 100.00
otbn_csr_aliasing 6.000s 15.908us 1 1 100.00
otbn_same_csr_outstanding 5.000s 78.770us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 11.000s 35.904us 1 1 100.00
otbn_dmem_err 31.000s 88.872us 1 1 100.00
internal_integrity 2 4 50.00
otbn_alu_bignum_mod_err 14.000s 98.925us 0 1 0.00
otbn_controller_ispr_rdata_err 8.000s 11.073us 1 1 100.00
otbn_mac_bignum_acc_err 10.000s 200.830us 1 1 100.00
otbn_urnd_err 11.000s 38.837us 0 1 0.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 9.000s 16.692us 1 1 100.00
otbn_mem_gnt_acc_err 0 1 0.00
otbn_mem_gnt_acc_err 101.000s 10002.699us 0 1 0.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 6.000s 44.923us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 228.000s 12085.391us 1 1 100.00
otbn_tl_intg_err 17.000s 75.135us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 83.000s 245.366us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 228.000s 12085.391us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 228.000s 12085.391us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 15.000s 48.254us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 31.000s 88.872us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 11.000s 35.904us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 17.000s 75.135us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 11.000s 23.618us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 11.000s 35.904us 1 1 100.00
otbn_dmem_err 31.000s 88.872us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 10.407us 1 1 100.00
otbn_illegal_mem_acc 9.000s 16.692us 1 1 100.00
otbn_sec_cm 228.000s 12085.391us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 228.000s 12085.391us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 8.000s 12.509us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 11.000s 35.904us 1 1 100.00
otbn_dmem_err 31.000s 88.872us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 10.407us 1 1 100.00
otbn_illegal_mem_acc 9.000s 16.692us 1 1 100.00
otbn_sec_cm 228.000s 12085.391us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 228.000s 12085.391us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 11.000s 23.618us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 11.000s 35.904us 1 1 100.00
otbn_dmem_err 31.000s 88.872us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 10.407us 1 1 100.00
otbn_illegal_mem_acc 9.000s 16.692us 1 1 100.00
otbn_sec_cm 228.000s 12085.391us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 228.000s 12085.391us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 8.000s 12.509us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 9.000s 22.803us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 10.000s 54.925us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 59.000s 359.083us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 59.000s 359.083us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 12.000s 18.076us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 228.000s 12085.391us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 228.000s 12085.391us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 14.000s 61.973us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 228.000s 12085.391us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 228.000s 12085.391us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 31.000s 71.541us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 31.000s 71.541us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 27.000s 80.497us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 8.000s 12.509us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 8.000s 12.509us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 8.000s 12.509us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 70.000s 1416.846us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 8.000s 12.509us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 8.000s 12.509us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 11.000s 78.705us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 8.000s 12.509us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 228.000s 12085.391us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 214.000s 3396.151us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_scoreboard.sv:440) [scoreboard] Check failed model_status == * (* [*] vs * [*]) Saw instruction when not in BUSY_EXECUTE operational state. 2 test runs
otbn_wfi_smoke 47266830946620921730834715072031403313442862185505457827875830416830314597807 115
UVM_INFO @ 15607498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_wfi_back_to_back 63526672165970533324649373925530415459617020521574822900229483362021891848965 114
UVM_INFO @ 17775848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal has unexpected timeout error 1 test run
otbn_alu_bignum_mod_err 71938346852259818381322888354916263712148120205137377973545417748090722660388 120
UVM_INFO @ 98925061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1297) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otbn_stress_all_with_rand_reset 35845692662093138594100985531679726577584798905883866821698073105977665159623 165
UVM_INFO @ 3396151374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,196): Assertion NotRunningWhenLocked_A has failed 1 test run
otbn_urnd_err 36639052169781684177273587535281696421789998635514741292137628192791466571670 115
UVM_ERROR @ 38836904 ps: (otbn_idle_checker.sv:196) [ASSERT FAILED] NotRunningWhenLocked_A
UVM_INFO @ 38836904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_mem_gnt_acc_err_vseq.sv:41) [otbn_mem_gnt_acc_err_vseq] timeout occurred! 1 test run
otbn_mem_gnt_acc_err 56060432919930895797112219293093397212035183123016935263515814064586213046848 110
UVM_INFO @ 10002699056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---