Simulation Results: otp_ctrl

 
09/09/2026 15:31:43 DVSim: v1.52.2 sha: 629146e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 67.75 %
  • code
  • 67.00 %
  • assert
  • 90.87 %
  • func
  • 45.37 %
  • line
  • 86.35 %
  • branch
  • 81.39 %
  • cond
  • 84.07 %
  • toggle
  • 51.27 %
  • FSM
  • 31.91 %
Validation stages
V1
100.00%
V2
55.00%
V2S
66.67%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.620s 814.066us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 7.930s 816.976us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 3.580s 284.683us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 2.650s 61.412us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 11.460s 1059.330us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 2.630s 68.355us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 3.140s 167.107us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 2.650s 61.412us 1 1 100.00
otp_ctrl_csr_aliasing 2.630s 68.355us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 2.340s 55.879us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 2.210s 99.442us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 127.690s 2910.651us 0 1 0.00
init_fail 0 1 0.00
otp_ctrl_init_fail 3.710s 194.126us 0 1 0.00
partition_check 0 2 0.00
otp_ctrl_background_chks 14.840s 2993.353us 0 1 0.00
otp_ctrl_check_fail 7.760s 173.316us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 7.300s 316.600us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 5.480s 433.620us 1 1 100.00
interface_key_check 0 1 0.00
otp_ctrl_parallel_key_req 10.890s 583.807us 0 1 0.00
lc_interactions 1 2 50.00
otp_ctrl_parallel_lc_req 17.010s 613.468us 0 1 0.00
otp_ctrl_parallel_lc_esc 7.530s 2170.848us 1 1 100.00
otp_dai_errors 0 1 0.00
otp_ctrl_dai_errs 13.400s 1038.262us 0 1 0.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 7.220s 656.224us 1 1 100.00
test_access 0 1 0.00
otp_ctrl_test_access 6.200s 555.118us 0 1 0.00
stress_all 0 1 0.00
otp_ctrl_stress_all 53.670s 3773.236us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 2.260s 43.465us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 3.010s 682.415us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 4.080s 136.146us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 4.080s 136.146us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.580s 284.683us 1 1 100.00
otp_ctrl_csr_rw 2.650s 61.412us 1 1 100.00
otp_ctrl_csr_aliasing 2.630s 68.355us 1 1 100.00
otp_ctrl_same_csr_outstanding 4.660s 148.921us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.580s 284.683us 1 1 100.00
otp_ctrl_csr_rw 2.650s 61.412us 1 1 100.00
otp_ctrl_csr_aliasing 2.630s 68.355us 1 1 100.00
otp_ctrl_same_csr_outstanding 4.660s 148.921us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 0 1 0.00
otp_ctrl_sec_cm 360.060s 50065.746us 0 1 0.00
tl_intg_err 1 2 50.00
otp_ctrl_sec_cm 360.060s 50065.746us 0 1 0.00
otp_ctrl_tl_intg_err 20.230s 826.143us 1 1 100.00
prim_count_check 0 1 0.00
otp_ctrl_sec_cm 360.060s 50065.746us 0 1 0.00
prim_fsm_check 0 1 0.00
otp_ctrl_sec_cm 360.060s 50065.746us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 20.230s 826.143us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 7.930s 816.976us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 7.930s 816.976us 1 1 100.00
sec_cm_dai_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 360.060s 50065.746us 0 1 0.00
sec_cm_kdi_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 360.060s 50065.746us 0 1 0.00
sec_cm_lci_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 360.060s 50065.746us 0 1 0.00
sec_cm_part_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 360.060s 50065.746us 0 1 0.00
sec_cm_scrmbl_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 360.060s 50065.746us 0 1 0.00
sec_cm_timer_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 360.060s 50065.746us 0 1 0.00
sec_cm_dai_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 360.060s 50065.746us 0 1 0.00
sec_cm_kdi_seed_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 360.060s 50065.746us 0 1 0.00
sec_cm_kdi_entropy_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 360.060s 50065.746us 0 1 0.00
sec_cm_lci_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 360.060s 50065.746us 0 1 0.00
sec_cm_part_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 360.060s 50065.746us 0 1 0.00
sec_cm_scrmbl_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 360.060s 50065.746us 0 1 0.00
sec_cm_timer_integ_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 360.060s 50065.746us 0 1 0.00
sec_cm_timer_cnsty_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 360.060s 50065.746us 0 1 0.00
sec_cm_timer_lfsr_redun 0 1 0.00
otp_ctrl_sec_cm 360.060s 50065.746us 0 1 0.00
sec_cm_dai_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 7.530s 2170.848us 1 1 100.00
otp_ctrl_sec_cm 360.060s 50065.746us 0 1 0.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.530s 2170.848us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.530s 2170.848us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.530s 2170.848us 1 1 100.00
otp_ctrl_macro_errs 7.220s 656.224us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.530s 2170.848us 1 1 100.00
sec_cm_timer_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 7.530s 2170.848us 1 1 100.00
otp_ctrl_sec_cm 360.060s 50065.746us 0 1 0.00
sec_cm_dai_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 7.530s 2170.848us 1 1 100.00
otp_ctrl_sec_cm 360.060s 50065.746us 0 1 0.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.530s 2170.848us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.530s 2170.848us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.530s 2170.848us 1 1 100.00
otp_ctrl_macro_errs 7.220s 656.224us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.530s 2170.848us 1 1 100.00
sec_cm_timer_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 7.530s 2170.848us 1 1 100.00
otp_ctrl_sec_cm 360.060s 50065.746us 0 1 0.00
sec_cm_part_data_reg_integrity 0 1 0.00
otp_ctrl_init_fail 3.710s 194.126us 0 1 0.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 7.760s 173.316us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 5.480s 433.620us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 5.480s 433.620us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 5.480s 433.620us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 5.480s 433.620us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 5.480s 433.620us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 7.930s 816.976us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 5.480s 433.620us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 7.930s 816.976us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 360.060s 50065.746us 0 1 0.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 7.300s 316.600us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 7.930s 816.976us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 7.930s 816.976us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 7.220s 656.224us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 73.890s 26181.476us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 12.040s 6236.935us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * 2 test runs
otp_ctrl_partition_walk 11503599665828226677946024413654415624138715272180751892364078432339245567867 160061
UVM_INFO @ 2910651469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 88108583721128330006648658523341535939874135393927357803362828493419104875018 1237
UVM_INFO @ 194125694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 2 test runs
otp_ctrl_parallel_key_req 39783541174796475451225730979984518089721513693694757708162113422671084747662 8469
UVM_INFO @ 583806620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 80505845884104345886000811972232786153046580877561677598138607563725306315269 1570
UVM_INFO @ 6236935431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 2 test runs
otp_ctrl_test_access 47506378091047275927287492317336493325479723991505564442659481564765465399032 3095
UVM_INFO @ 555118286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 35370147794882827973800109342924529469454882682136176496348997996960488758534 21537
UVM_INFO @ 3773236103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_low_freq_read 32744421163324763578654472458600931784433428937231220304038133802622993138224 95
UVM_INFO @ 26181476162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1375) [otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger! 1 test run
otp_ctrl_background_chks 114897955289125549336024406668680143797274434126473196506793087359282653593608 4622
UVM_INFO @ 2993352632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:961) [scoreboard] Check failed (csr.get_mirrored_value() | status_mask) == (item.d_data | status_mask) (* [*] vs * [*]) reg name: status, compare_mask * 1 test run
otp_ctrl_parallel_lc_req 13989170050543448963973797136379727381527296264974065428355142156352837843021 9653
UVM_INFO @ 613468320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:419) scoreboard [scoreboard] Waited * cycles but did not see alert fatal_check_error. (Max wait calculated ALERT_B2B_DELAY + max_delay + * = * + * + *) 1 test run
otp_ctrl_dai_errs 44528268977106510198773038324869101121872848851609541992754912001071390480544 6817
UVM_INFO @ 1038261702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_check_error has unexpected timeout error 1 test run
otp_ctrl_check_fail 111615179374476167951164271462128280739316493894651787874201206287592818641099 4119
UVM_INFO @ 173315513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [otp_ctrl_common_vseq] Expected alert (fatal_check_error) did not fire in * cycles. 1 test run
otp_ctrl_sec_cm 50178255794609530718927798546324424299469837282067658129759220865415255926927 2792
UVM_INFO @ 50065745659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---