Simulation Results: rstmgr

 
09/09/2026 15:31:43 DVSim: v1.52.2 sha: 629146e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.56 %
  • code
  • 99.21 %
  • assert
  • 97.99 %
  • func
  • 92.47 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.41 %
  • toggle
  • 99.52 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.910s 79.192us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.360s 64.447us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 1.300s 37.631us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 4.430s 80.261us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.260s 38.988us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.950s 95.735us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 1.300s 37.631us 1 1 100.00
rstmgr_csr_aliasing 1.260s 38.988us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.470s 62.792us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.500s 39.552us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.150s 54.490us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 9.170s 744.633us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 9.170s 744.633us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 9.170s 744.633us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 9.170s 744.633us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 31.230s 3198.634us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.020s 42.583us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.100s 62.736us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.100s 62.736us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.360s 64.447us 1 1 100.00
rstmgr_csr_rw 1.300s 37.631us 1 1 100.00
rstmgr_csr_aliasing 1.260s 38.988us 1 1 100.00
rstmgr_same_csr_outstanding 1.390s 40.891us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.360s 64.447us 1 1 100.00
rstmgr_csr_rw 1.300s 37.631us 1 1 100.00
rstmgr_csr_aliasing 1.260s 38.988us 1 1 100.00
rstmgr_same_csr_outstanding 1.390s 40.891us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 24.000s 3389.719us 1 1 100.00
rstmgr_tl_intg_err 4.090s 323.509us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 24.000s 3389.719us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 24.000s 3389.719us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 4.090s 323.509us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.570s 59.991us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 3.880s 424.863us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 3.360s 292.230us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 24.000s 3389.719us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 1.300s 37.631us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 1.300s 37.631us 1 1 100.00