Simulation Results

Simulation Results: rv_dm/use_dmi_interface

09/09/2026 15:31:43 DVSim: v1.52.2 sha: 629146e json Branch: master Tool: xcelium [24.03-s007]

Coverage statistics

Total
87.59 %

code
73.42 %

assert
96.66 %

func
92.68 %

block
89.47 %

line
89.37 %

branch
71.41 %

toggle
72.19 %

FSM
60.71 %

Validation stages

V1		92.59%
V2		69.57%
V2S		100.00%
V3		0.00%
unmapped		0.00%

25/27 passed

92.59 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	47.000s	1189.839us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	50.000s	162.331us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	42.000s	99.955us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	48.000s	7039.431us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	39.000s	106.946us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	45.000s	9560.710us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	44.000s	4693.510us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	53.000s	2435.578us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	60.000s	5603.952us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	41.000s	817.501us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	45.000s	177.398us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	49.000s	142.686us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	46.000s	110.967us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	48.000s	241.158us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	37.000s	321.146us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	52.000s	248.824us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	50.000s	613.294us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	41.000s	817.501us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	49.000s	187.804us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	52.000s	432.780us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	49.000s	142.686us	1	1	100.00
rom_read_access				0	1	0.00
	rv_dm_rom_read_access	46.000s	49.961us	0	1	0.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	50.000s	409.589us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	44.000s	128.214us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	109.000s	31557.253us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	51.000s	4587.803us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	46.000s	146.879us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	51.000s	4587.803us	1	1	100.00
	rv_dm_csr_rw	44.000s	128.214us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	51.000s	83.583us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	46.000s	93.597us	1	1	100.00

16/23 passed

69.57 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	47.000s	1189.839us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	46.000s	746.264us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	51.000s	316.631us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	37.000s	123.729us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	46.000s	806.056us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	51.000s	1575.970us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	48.000s	63.848us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	45.000s	2997.867us	0	1	0.00
sba_autoincrement				0	1	0.00
	rv_dm_autoincr_sba_tl_access	36.000s	112.705us	0	1	0.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	52.000s	170.847us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	37.000s	1312.695us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	47.000s	102.857us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	47.000s	108.254us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm	64.000s	6922.948us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	69.000s	3200.769us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	51.000s	91.198us	1	1	100.00
stress_all				0	1	0.00
	rv_dm_stress_all	39.000s	69.647us	0	1	0.00
alert_test				1	1	100.00
	rv_dm_alert_test	45.000s	39.349us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	44.000s	1412.262us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	44.000s	1412.262us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	51.000s	4587.803us	1	1	100.00
	rv_dm_csr_hw_reset	50.000s	409.589us	1	1	100.00
	rv_dm_csr_rw	44.000s	128.214us	1	1	100.00
	rv_dm_same_csr_outstanding	38.000s	190.217us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	51.000s	4587.803us	1	1	100.00
	rv_dm_csr_hw_reset	50.000s	409.589us	1	1	100.00
	rv_dm_csr_rw	44.000s	128.214us	1	1	100.00
	rv_dm_same_csr_outstanding	38.000s	190.217us	1	1	100.00

V2S

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_sec_cm	44.000s	651.657us	1	1	100.00
	rv_dm_tl_intg_err	55.000s	1255.204us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	55.000s	1255.204us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	37.000s	1312.695us	1	1	100.00
	rv_dm_debug_disabled	51.000s	72.265us	1	1	100.00
sec_cm_lc_dft_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	37.000s	1312.695us	1	1	100.00
	rv_dm_debug_disabled	51.000s	72.265us	1	1	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	47.000s	1189.839us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				1	1	100.00
	rv_dm_buffered_enable	46.000s	161.408us	1	1	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	42.000s	304.606us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	42.000s	304.606us	1	1	100.00
sec_cm_exec_ctrl_mubi				1	1	100.00
	rv_dm_buffered_enable	46.000s	161.408us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	rv_dm_stress_all_with_rand_reset	43.000s	178.721us	0	1	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	713.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_scoreboard.sv:481) [scoreboard] sba_tl_access_q item uncompared:				2 test runs
	rv_dm_sba_tl_access	54731175599388009295173866797582529292216385878268876395360374441883549054279	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23844
	rv_dm_bad_sba_tl_access	40424416057244372795777521535472427145756794159780344530189602565565771994348	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23816
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				2 test runs
	rv_dm_delayed_resp_sba_tl_access	96422300636618490882063065185891757474144843633787053469359987057904710575029	107	UVM_INFO @ 63847867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	17835550936701504990890455126204570902373125921901771816613587212704600950401	107	UVM_INFO @ 112705435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				2 test runs
	rv_dm_hart_unavail	93323987278857898481665983811550188075331187249725841688459643612091414213025	87	UVM_INFO @ 108253758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	89655018892821532903105200384134530505465947755300706910007056136203776480030	88	UVM_INFO @ 69646840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				2 test runs
	rv_dm_jtag_dmi_debug_disabled	93290659158047975128018104419523904254187045770994725938724660361253676479084	87	UVM_INFO @ 170846542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	18871500010196417323722281872910219431781784575412103072163912953177292101700	91	UVM_INFO @ 178721125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				1 test run
	rv_dm_mem_tl_access_resuming	97623804504188044510760459075528527223223959440963424596178760127857956834169	87	UVM_INFO @ 110966688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:409) scoreboard [scoreboard] Unexpected response to read from address * in mem reg block. Problems: '{"Expected read d_data=, but it was "}. Item: (req: (cip_tl_seq_item@23887) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }				1 test run
	rv_dm_rom_read_access	58198521755557219055142227067366426942378212886112730071260783724667663429464	87	). UVM_INFO @ 49960792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				1 test run
	rv_dm_scanmode	58069703686882610177055136721732710041297198504420900077387187952229656316205	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---